H5GQ1H24AFR-R0C datasheet(88/173 Pages) HYNIX

88 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

H5GQ1H24AFR

When enabled by the RDCRC flag in MR4, EDC data is returned to the controller with a latency of (CLmrs

+ CRCRL) * tCK + tWCK2CKPIN + tWCK2CK + tWCK2DQO, where CRCRL is the CRC Read latency pro‐

grammed in MR4.

Figure 55. READ Word Lane Timing

CK#

tCH

tCL

tCK

CLmrs

DQ/DBI#/EDC

(mean)

WCK#

WCK

tWCK2CKPIN + tWCK2CK

tWCK2DQO

DQ/DBI#/EDC

(first bit)

DQ/DBI#/EDC

(last bit)

tDQDQO(min)

tDQDQO(max)

1) CLmrs is the CAS latency programmed in Mode Register MR0.

2) Timings are shown with positive tWCK2CKPIN and tWCK2CK values. See WCK2CK timings for

tWCK2CKPIN and tWCK2CK ranges.

3) tWCK2DQO parameter values could be negative or positive numbers, depending on PLL‐on or PLL‐off mode

operation and design implementation. They also vary across PVT. Data training is required to determine

the actual tWCK2DQO value for stable READ operation.

4) tDQDQO defines the minimum to maximum variation of tWCK2DQO within a double byte (x32 mode) or

a single byte (x16 mode).

5) tDQDQO also applies for CRC data from WRITE and READ commands with CRC enabled, the EDC hold

D1 D2 D3 D4 D5 D6 D7

Case 1: Negative tWCK2DQO

DQ/DBI#/EDC

(mean)

tWCK2DQO

DQ/DBI#/EDC

(first bit)

DQ/DBI#/EDC

(last bit)

tDQDQO(min)

tDQDQO(max)

D1 D2 D3 D4 D5 D6 D7

Case 2: Positive tWCK2DQO

Donʹt Care

pattern, and the data strobe in RDQS mode.

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