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H5GQ1H24AFR-R0C 데이터시트(PDF) 48 Page - Hynix Semiconductor

부품명 H5GQ1H24AFR-R0C
상세설명  1Gb (32Mx32) GDDR5 SGRAM
PDF  173 Pages
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제조업체  HYNIX [Hynix Semiconductor]
홈페이지  http://www.skhynix.com/kor/main.do
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H5GQ1H24AFR-R0C 데이터시트(HTML) 48 Page - Hynix Semiconductor

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This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsability for use of circuits described. No patent licenses are implied.
Rev. 1.0 /Nov. 2009
48
H5GQ1H24AFR
 4.3. MODE REGISTER 2 (MR2)
Mode Register 2 defines the output driver (OCD) and termination offsets as shown in Figure 25.
Mode  Register  2  is  programmed  via  the  MODE  REGISTER  SET  (MRS)  command  with  BA0=0,  BA1=1,
BA2=0 and BA3=0.
Figure 25. Mode Register 2 (MR2) Definition
Impedance Offsets
The driver and termination impedances may be offset individually for PD driver, PU driver, DQ/DBI#/
WCK  termination  and  address/command  termination.  The  offset  impedance  step  values  may  be  non‐
linear and will vary across PVT. With negative offset steps the drive strengths will be decreased and Ron
BA3 BA2 BA1 BA0
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
00
10
0
ADR/CMD 
Termination Offset
Data and WCK 
Termination Offset
OCD Pullup 
Driver Offset
OCD Pulldown 
Driver Offset
A2
A1
A0
OCD Pulldown 
Driver Offset
00
0
0
00
1
+1
01
0
+2
01
1
+3
10
0
‐4
10
1
‐3
11
0
‐2
11
1
‐1
A5
A4
A3
OCD Pullup 
Driver Offset
00
0
0
00
1
+1
01
0
+2
01
1
+3
10
0
‐4
10
1
‐3
11
0
‐2
11
1
‐1
A8
A7
A6
Data and WCK 
Termination Offset
00
0
0
00
1
+1
01
0
+2
01
1
+3
10
0
‐4
10
1
‐3
11
0
‐2
11
1
‐1
A11
A10
A9
ADR/CMD 
Termination Offset
00
0
0
00
1
+1
01
0
+2
01
1
+3
10
0
‐4
10
1
‐3
11
0
‐2
11
1
‐1



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