H5GQ1H24AFR-R0C datasheet(102/173 Pages) HYNIX

102 / 173 page

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsability for use of circuits described. No patent licenses are implied.

Rev. 1.0 /Nov. 2009

102

H5GQ1H24AFR

EDC Pin Special Function Overview

The EDC pin is used for many different functions. The behavior of the EDC pin in various modes is sum‐

marized in Table 26.

Table 26 EDC Pin Behavior

Device Status

Condition

EDC0‐EDC3 Pin Status

Device Power‐up

RESET# = LOW

Hi‐Z

RESET# = HIGH; no WCK clocks

High

RESET# = HIGH; stable WCK clocks

EDC hold pattern (default = ’1111’)

WCK2CK Training

WCK is sampled High

EDC hold pattern (’1111’)

WCK is sampled Low

Inverted EDC hold pattern (’0000’)

Idle

EDC13inv MR4 A11=0

EDC hold pattern

EDC13inv MR4 A11=1

EDC0, EDC2: EDC hold pattern

EDC1, EDC3: inverted EDC hold pattern

WRITE Burst

WRCRC on

CRC data

WRCRC off

EDC hold pattern

READ or RDTR burst

RDCRC on

CRC data

RDCRC off

EDC hold pattern

LDFF

WRCRC + RDCRC both on or both off

EDC hold pattern

WRTR burst

‐

EDC hold pattern

Power‐Down

WCK enabled (MR5 A1=0)

EDC hold pattern

WCK disabled during Power‐Down

using MR5 A1=1

High

Self Refresh

‐

High

Read Burst in RDQS Mode

MR3 A5=1

Fixed ’1010’ strobe pattern with 4 U.I.

preamble

READ burst in RDQS Mode with

RDQS pseudo‐differential

MR3 A5=1; EDC13inv MR4 A11=1

EDC0, EDC2: Fixed ’1010’ strobe pattern

with 4 U.I. preamble

EDC1, EDC3: Fixed ’0101’ strobe pattern

with 4 U.I. preamble

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