MPC8309EC datasheet(32/82 Pages) FREESCALE

32 / 82 page

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

TDM/SI

9.2

TDM/SI AC Timing Specifications

Table 29 provides the TDM/SI input and output AC timing specifications.

Figure 20 provides the AC test load for the TDM/SI.

Figure 20. TDM/SI AC Test Load

Table 29. TDM/SI AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

TDM/SI outputs—External clock delay

tSEKHOV

214

TDM/SI outputs—External clock High Impedance

tSEKHOX

210

TDM/SI inputs—External clock input setup time

tSEIVKH

5—

TDM/SI inputs—External clock input hold time

tSEIXKH

2—

Notes:

1. Output specifications are measured from the 50% level of the rising edge of QE_CLK_IN to the 50% level of the signal.

Timings are measured at the pin.

2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSEKHOX symbolizes the TDM/SI

outputs external timing (SE) for the time tTDM/SI memory clock reference (K) goes from the high state (H) until outputs (O)

are invalid (X).

Output

Z0 = 50 

OVDD/2

RL = 50 

MPC8309EC 데이터시트(PDF) 32 Page - Freescale Semiconductor, Inc