MPC8309EC datasheet(38/82 Pages) FREESCALE

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

USB

Figure 28 and Figure 29 provide the AC test load and signals for the USB, respectively.

Figure 28. USB AC Test Load

Figure 29. USB Signals

Table 36. USB General Timing Parameters

Parameter

Symbol1

Min

Max

Unit

Notes

USB clock cycle time

tUSCK

—

Input setup to USB clock—all inputs

tUSIVKH

4—

input hold to USB clock—all inputs

tUSIXKH

1—

USB clock to output valid—all outputs (except

USBDR_STP_USBDR_STP)

tUSKHOV

—7

USB clock to output valid—USBDR_STP

tUSKHOV

—7.5

Output hold from USB clock—all outputs

tUSKHOX

2—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing

(USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX

symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X) or

output hold time.

Output

Z0 = 50 

OVDD/2

RL = 50 

Output Signals

tUSKHOV

USBDR_CLK

Input Signals

tUSIXKH

tUSIVKH

tUSKHOX

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