MPC8309EC datasheet(71/82 Pages) FREESCALE

부품명	MPC8309EC

상세설명	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

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제조업체	FREESCALE [Freescale Semiconductor, Inc]

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Clocking

NOTE

Core VCO frequency = core frequency

 VCO divider. The VCO divider

(RCWL[COREPLL[0:1]]), must be set properly so that the core VCO

frequency is in the range of 400–800 MHz.

23.6

QUICC Engine PLL Configuration

The QUICC Engine PLL is controlled by the RCWL[CEPMF] and RCWL[CEPDF] parameters. Table 61

shows the multiplication factor encodings for the QUICC Engine PLL.

The RCWL[CEVCOD] denotes the QUICC Engine PLL VCO internal frequency as shown in Table 62.

0011

3:1

 4

0011

3:1

 8

0011

3:1

 8

Table 61. QUICC Engine PLL Multiplication Factors

RCWL[CEPMF]

RCWL[CEPDF]

QUICC Engine PLL Multiplication Factor = RCWL[CEPMF]/

(1 + RCWL[CEPDF)

00000–00001

Reserved

00010

 2

00011

 3

00100

 4

00101

 5

00110

 6

00111

 7

01000

 8

01001–11111

Reserved

Table 62. QUICC Engine PLL VCO Divider

RCWL[CEVCOD]

VCO Divider

Reserved

Table 60. e300 Core PLL Configuration (continued)

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider

0-1

2-5

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