MPC8309EC datasheet(76/82 Pages) FREESCALE

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

System Design Information

lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.

If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic

surfaces and its performance verified under the application requirements.

24.2.1

Experimental Determination of the Junction Temperature with a

Heat Sink

When heat sink is used, the junction temperature is determined from a thermocouple inserted at the

interface between the case of the package and the interface material. A clearance slot or hole is normally

required in the heat sink. Minimizing the size of the clearance is important to minimize the change in

thermal performance caused by removing part of the thermal interface to the heat sink. Because of the

experimental difficulties with this technique, many engineers measure the heat sink temperature and then

back calculate the case temperature using a separate measurement of the thermal resistance of the

interface.

From this case temperature, the junction temperature is determined from the junction-to-case thermal

resistance using the following equation:

TJ = TC +(RJC  PD)

Eqn. 5

where:

TC = case temperature of the package (C)

RJC = junction-to-case thermal resistance (C/W)

PD = power dissipation (W)

25 System Design Information

This section provides electrical and thermal design recommendations for successful application of the

MPC8309.

25.1

System Clocking

The MPC8309 includes three PLLs.

•

The system PLL (AVDD2) generates the system clock from the externally supplied SYS_CLK_IN

input. The frequency ratio between the system and SYS_CLK_IN is selected using the system PLL

ratio configuration bits as described in Section 23.4, “System PLL Configuration.”

•

The e300 core PLL (AVDD3) generates the core clock as a slave to the system clock. The frequency

ratio between the e300 core clock and the system clock is selected using the e300 PLL ratio

configuration bits as described in Section 23.5, “Core PLL Configuration.”

•

The QUICC Engine PLL (AVDD1) which uses the same reference as the system PLL. The QUICC

Engine block generates or uses external sources for all required serial interface clocks.

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