MPC8309EC datasheet(33/82 Pages) FREESCALE

33 / 82 page

MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

HDLC

Figure 21 represents the AC timing from Table 29. Note that although the specifications generally

reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the

active edge.

Figure 21. TDM/SI AC Timing (External Clock) Diagram

10 HDLC

This section describes the DC and AC electrical specifications for the high level data link control (HDLC),

of the MPC8309.

10.1

HDLC DC Electrical Characteristics

Table 30 provides the DC electrical characteristics for the MPC8309 HDLC protocol.

10.2

HDLC AC Timing Specifications

Table 31 provides the input and output AC timing specifications for HDLC protocol.

Table 30. HDLC DC Electrical Characteristics

Characteristic

Symbol

Condition

Min

Max

Unit

Output high voltage

VOH

IOH = –2.0 mA

2.4

—

Output low voltage

VOL

IOL = 3.2 mA

—

0.5

Input high voltage

VIH

—2.0

OVDD +0.3

Input low voltage

VIL

—–0.3

0.8

Input current

IIN

0 V

 V

IN OVDD

—

±5

A

Table 31. HDLC AC Timing Specifications1

Characteristic

Symbol2

Min

Max

Unit

Outputs—Internal clock delay

tHIKHOV

Outputs—External clock delay

tHEKHOV

Outputs—Internal clock high impedance

tHIKHOX

05.5

TDM/SICLK (Input)

tSEIXKH

tSEIVKH

tSEKHOV

Input Signals:

TDM/SI

(See Note)

Output Signals:

TDM/SI

(See Note)

Note: The clock edge is selectable on TDM/SI.

tSEKHOX

MPC8309EC 데이터시트(PDF) 33 Page - Freescale Semiconductor, Inc

MPC8309EC 데이터시트(HTML) 33 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

데이터시트 다운로드

링크 URL