MPC8309EC datasheet(70/82 Pages) FREESCALE

부품명	MPC8309EC

상세설명	PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications

PDF	82 Pages

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제조업체	FREESCALE [Freescale Semiconductor, Inc]

홈페이지	http://www.freescale.com

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MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 0

Freescale Semiconductor

Clocking

23.5

Core PLL Configuration

RCWL[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the e300

core clock (core_clk). Table 60 shows the encodings for RCWL[COREPLL]. COREPLL values not listed

in Table 60 should be considered reserved.

Table 59. CSB Frequency Options

SPMF

csb_clk : sys_clk_in Ratio

PCI_SYNC_IN(MHz)

33.33

66.67

csb_clk Frequency (MHz)

0010

2:1

133

0011

3:1

0100

4:1

133

0101

5:1

125

167

0110

6:1

Table 60. e300 Core PLL Configuration

RCWL[COREPLL]

core_clk : csb_clk Ratio

VCO Divider

0-1

2-5

0000

PLL bypassed

(PLL off, csb_clk clocks core directly)

PLL bypassed

(PLL off, csb_clk clocks core directly)

0001

1:1

2

0001

1:1

4

0001

1:1

8

0001

1:1

8

0001

1.5:1

 2

0001

1.5:1

 4

0001

1.5:1

 8

0001

1.5:1

 8

0010

2:1

 2

0010

2:1

 4

0010

2:1

 8

0010

2:1

 8

0010

2.5:1

 2

0010

2.5:1

 4

0010

2.5:1

 8

0010

2.5:1

 8

0011

3:1

 2

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