| 전자부품 데이터시트 검색엔진 |
|
COP8SE 데이터시트(PDF) 32 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
COP8SE 데이터시트(HTML) 32 Page - National Semiconductor (TI) |
|
32 / 47 page ![]() 10.0 MICROWIRE/PLUS (Continued) 10.1.2 MICROWIRE/PLUS Slave Mode Operation In the MICROWIRE/PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and re- setting the appropriate bits in the Port G configuration regis- ter. Table 9 summarizes the settings required to enter the Slave mode of operation. TABLE 9. MICROWIRE/PLUS Mode Settings This table assumes that the control flag MSEL is set. G4 (SO) G5 (SK) G4 G5 Operation Config. Bit Config. Bit Fun. Fun. 1 1 SO Int. MICROWIRE/PLUS SK Master 0 1 TRI- Int. MICROWIRE/PLUS STATE SK Master 1 0 SO Ext. MICROWIRE/PLUS SK Slave 0 0 TRI- Ext. MICROWIRE/PLUS STATE SK Slave The user must set the BUSY flag immediately upon entering the Slave mode. This ensures that all data bits sent by the Master is shifted properly. After eight clock pulses the BUSY flag is clear, the shift clock is stopped, and the sequence may be repeated. 10.1.3 Alternate SK Phase Operation and SK Idle Polarity The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. In both the modes the SK idle polarity can be either high or low. The polarity is selected by bit 5 of Port G data register. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on the ris- ing edge of the SK clock. Bit 6 of Port G configuration regis- ter selects the SK edge. A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting SKSEL causes the MICROWIRE/PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag selects the alter- nate SK clock. The SKSEL is mapped into the G6 configura- tion bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal. TABLE 10. MICROWIRE/PLUS Shift Clock Polarity and Sample/Shift Phase Port G SK Phase G6 (SKSEL) Config. Bit G5 Data Bit SO Clocked Out On: SI Sampled On: SK Idle Phase Normal 0 0 SK Falling Edge SK Rising Edge Low Alternate 1 0 SK Rising Edge SK Falling Edge Low Alternate 0 1 SK Rising Edge SK Falling Edge High Normal 1 1 SK Falling Edge SK Rising Edge High DS100973-33 FIGURE 22. MICROWIRE/PLUS SPI Mode Interface Timing, Normal SK Mode, SK Idle Phase being Low DS100973-34 FIGURE 23. MICROWIRE/PLUS SPI Mode Interface Timing, Alternate SK Mode, SK Idle Phase being Low www.national.com 32 |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |