COP8SE datasheet(34/47 Pages) NSC

34 / 47 page

11.0 Memory Map

All RAM, ports and registers (except A and PC) are mapped into data memory address space.

Address

Contents

S/ADD REG

0000 to 006F

On-Chip RAM bytes (112 bytes)

0070 to 007F

Unused RAM Address Space (Reads

As All Ones)

xx80 to xxBF

Unused RAM Address Space (Reads

Undefined Data)

xxC7

WATCHDOG Service Register

(Reg:WDSVR)

xxC8

MIWU Edge Select Register

(Reg:WKEDG)

xxC9

MIWU Enable Register (Reg:WKEN)

xxCA

MIWU Pending Register

(Reg:WKPND)

xxCB

Reserved

xxCC

Reserved

xxCD to xxCE

Reserved

xxCF

Idle Timer Window Length (Reg:ITMR)

xxD0

Port L Data Register

xxD1

Port L Configuration Register

xxD2

Port L Input Pins (Read Only)

xxD3

Reserved

xxD4

Port G Data Register

xxD5

Port G Configuration Register

xxD6

Port G Input Pins (Read Only)

xxD7 to xxDF

Reserved

xxE0

EERAM Control Register E2CFG

xxE1 to xxE5

Reserved for EE Control Registers

xxE6

Timer T1 Autoload Register T1RB

Lower Byte

xxE7

Timer T1 Autoload Register T1RB

Upper Byte

xxE8

ICNTRL Register

xxE9

MICROWIRE/PLUS Shift Register

xxEA

Timer T1 Lower Byte

xxEB

Timer T1 Upper Byte

xxEC

Timer T1 Autoload Register T1RA

Lower Byte

xxED

Timer T1 Autoload Register T1RA

Upper Byte

xxEE

CNTRL Control Register

xxEF

PSW Register

xxF0 to xxFB

On-Chip RAM Mapped as Registers

xxFC

X Register

xxFD

SP Register

xxFE

B Register

xxFF

S Register

0100–017F

On-Chip 128 EERAM Bytes

Note: Reading memory locations 0070H–007FH (Segment 0) will return all

ones. Reading unused memory locations 0080H–00BFH (Segment 0)

will return undefined data. Reading memory locations from other Seg-

ments (i.e., Segment 2, Segment 3, … etc.) will return undefined data.

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