COP8SE datasheet(17/47 Pages) NSC

17 / 47 page

6.0 Timers (Continued)

6.2.2 Mode 2. External Event Counter Mode

This mode is quite similar to the processor independent

PWM mode previously described. The main difference is that

the timer, T1, is clocked by the input signal from the T1A pin.

The T1 timer control bits, T1C3, T1C2 and T1C1 allow the

timer to be clocked either on a positive or negative edge from

the T1A pin. Underflows from the timer are latched into the

T1PNDA pending flag. Setting the T1ENA control flag will

cause an interrupt when the timer underflows.

In this mode the input pin T1B can be used as an indepen-

dent positive edge sensitive interrupt input if the T1ENB con-

trol flag is set. The occurrence of a positive edge on the T1B

input pin is latched into the T1PNDB flag.

Figure 13 shows a block diagram of the timer in External

Event Counter mode.

Note: The PWM output is not available in this mode since the T1A pin is be-

ing used as the counter input clock.

6.2.3 Mode 3. Input Capture Mode

The device can precisely measure external frequencies or

time external events by placing the timer block, T1, in the in-

put capture mode.

In this mode, the timer T1 is constantly running at the fixed t

rate. The two registers, R1A and R1B, act as capture regis-

ters. Each register acts in conjunction with a pin. The register

R1A acts in conjunction with the T1A pin and the register

R1B acts in conjunction with the T1B pin.

The timer value gets copied over into the register when a

trigger event occurs on its corresponding pin. Control bits,

T1C3, T1C2 and T1C1, allow the trigger events to be speci-

fied either as a positive or a negative edge. The trigger con-

dition for each input pin can be specified independently.

The trigger conditions can also be programmed to generate

interrupts. The occurrence of the specified trigger condition

on the T1A and T1B pins will be respectively latched into the

pending flags, T1PNDA and T1PNDB. The control flag

T1ENA allows the interrupt on T1A to be either enabled or

disabled. Setting the T1ENA flag enables interrupts to be

generated when the selected trigger condition occurs on the

T1A pin. Similarly, the flag T1ENB controls the interrupts

from the T1B pin.

Underflows from the timer can also be programmed to gen-

erate interrupts. Underflows are latched into the timer T1C0

pending flag (the T1C0 control bit serves as the timer under-

flow interrupt pending flag in the Input Capture mode). Con-

sequently, the T1C0 control bit should be reset when enter-

ing the Input Capture mode. The timer underflow interrupt is

enabled with the T1ENA control flag. When a T1A interrupt

occurs in the Input Capture mode, the user must check both

the T1PNDA and T1C0 pending flags in order to determine

whether a T1A input capture or a timer underflow (or both)

caused the interrupt.

Figure 14 shows a block diagram of the timer in Input Cap-

ture Mode.

DS100973-46

FIGURE 12. Timer in PWM Mode

DS100973-47

FIGURE 13. Timer in External Event Counter Mode

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