COP8SE datasheet(16/47 Pages) NSC

16 / 47 page

6.0 Timers (Continued)

6.2 TIMER T1

The device has a powerful timer/counter block. The timer

consists of a 16-bit timer, T1, and two supporting 16-bit

autoreload/capture registers, R1A and R1B. The timer block

has two pins associated with it, T1A and T1B. The pin T1A

supports I/O required by the timer block, while the pin T1B is

an input to the timer block. The powerful and flexible timer

block allows the device to easily perform all timer functions

with minimal software overhead. The timer block has three

operating modes: Processor Independent PWM mode, Ex-

ternal Event Counter mode, and Input Capture mode.

The control bits T1C3, T1C2, and T1C1 allow selection of the

different modes of operation.

6.2.1 Mode 1. Processor Independent PWM Mode

As the name suggests, this mode allows the device to gen-

erate a PWM signal with very minimal user intervention. The

user only has to define the parameters of the PWM signal

(ON time and OFF time). Once begun, the timer block will

continuously generate the PWM signal completely indepen-

dent of the microcontroller. The user software services the

timer block only when the PWM parameters require updat-

ing.

In this mode the timer T1 counts down at a fixed rate of t

Upon every underflow the timer is alternately reloaded with

the contents of supporting registers, R1A and R1B. The very

first underflow of the timer causes the timer to reload from

the register R1A. Subsequent underflows cause the timer to

be reloaded from the registers alternately beginning with the

The T1 Timer control bits, T1C3, T1C2 and T1C1 set up the

timer for PWM mode operation.

Figure 12 shows a block diagram of the timer in PWM mode.

The underflows can be programmed to toggle the T1A output

pin. The underflows can also be programmed to generate in-

terrupts.

Underflows from the timer are alternately latched into two

pending flags, T1PNDA and T1PNDB. The user must reset

these pending flags under software control. Two control en-

able flags, T1ENA and T1ENB, allow the interrupts from the

timer underflow to be enabled or disabled. Setting the timer

enable flag T1ENA will cause an interrupt when a timer un-

derflow causes the R1A register to be reloaded into the

timer. Setting the timer enable flag T1ENB will cause an in-

terrupt when a timer underflow causes the R1B register to be

reloaded into the timer. Resetting the timer enable flags will

disable the associated interrupts.

Either or both of the timer underflow interrupts may be en-

abled. This gives the user the flexibility of interrupting once

per PWM period on either the rising or falling edge of the

PWM output. Alternatively, the user may choose to interrupt

on both edges of the PWM output.

DS100973-52

FIGURE 11. Functional Block Diagram for Idle Timer T0

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