TNETV2501INPGF datasheet(142/197 Pages) TI1

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Electrical Specifications

142

December 2002 − Revised November 2008

SPRS206K

5.6.3 Clock Generation in Bypass Mode (APLL Synthesis Disabled)

Table 5−2 and Table 5−3 assume testing over recommended operating conditions (see Figure 5−3).

Table 5−2. CLKIN in Bypass Mode Timing Requirements

NO.

MIN

MAX

UNIT

tc(CI)

Cycle time, CLKIN†

APLL Synthesis Disabled

‡

tf(CI)

Fall time, CLKIN

tr(CI)

Rise time, CLKIN

C10

tw(CIL)

Pulse duration, CLKIN low

0.4 *tc(CI)

C11

tw(CIH) Pulse duration, CLKIN high

0.4 *tc(CI)

† If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5−1.

‡ This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

Table 5−3. CLKOUT in Bypass Mode Switching Characteristics

NO.

PARAMETER

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

K * tc(CI)§

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

K * tc(CI)/2 − 1

K * tc(CI)/2 + 1

tw(COH)

Pulse duration, CLKOUT high

K * tc(CI)/2 − 1

K * tc(CI)/2 + 1

§ K = divider ratio between CPU clock and system clock selected as CLKOUT. For example, when SYSCLK1 is selected as CLKOUT and SYSCLK1

is set to the CPU clock divided by four, use K = 4.

¶ This device utilizes a fully static design and therefore can operate with tc(CI) approaching ∞. The device is characterized at frequencies

approaching 0 Hz.

CLKOUT

CLKIN

C10

C11

NOTE: The relationship of CLKIN to CLKOUT depends on the system clock selected to drive CLKOUT. The waveform relationship shown in

Figure 5−3 is intended to illustrate the timing parameters only and may differ based on configuration.

Figure 5−3. Bypass Mode Clock Timings

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