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TNETV2501INPGF 데이터시트(PDF) 143 Page - Texas Instruments |
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TNETV2501INPGF 데이터시트(HTML) 143 Page - Texas Instruments |
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143 / 197 page ![]() Electrical Specifications 143 December 2002 − Revised November 2008 SPRS206K 5.6.4 Clock Generation in Lock Mode (APLL Synthesis Enabled) The frequency of the reference clock provided at the CLKIN pin can be multiplied by a synthesis factor of N to generate the internal CPU clock cycle. The synthesis factor is determined by: N + M D 0 where: M = the multiply factor set in the PLLM field of the PLL Multiplier Control Register (PLLM) D0 = the divide factor set in the PLLDIV0 field of the PLL Divider 0 Register (PLLDIV0) Valid values for M are (multiply by) 2 to 15. Valid values for D0 are (divide by) 1 to 32. For detailed information on clock generation configuration, see Section 3.9, System Clock Generator. Table 5−4 and Table 5−5 assume testing over recommended operating conditions (see Figure 5−4). Table 5−4. CLKIN in Lock Mode Timing Requirements NO. MIN MAX UNIT C7 tc(CI) Cycle time, CLKIN† APLL synthesis enabled 10‡ 83.3 ns C8 tf(CI) Fall time, CLKIN 10 ns C9 tr(CI) Rise time, CLKIN 10 ns † If an external crystal is used, the X2/CLKIN cycle time is limited by the crystal frequency range listed in Table 5−1. ‡ The clock frequency synthesis factor and minimum CLKIN cycle time should be chosen such that the resulting CLKOUT cycle time is within the specified range [tc(CO)]. Table 5−5. CLKOUT in Lock Mode Switching Characteristics NO. PARAMETER MIN TYP MAX UNIT C1 tc(CO) Cycle time, CLKOUT 6.66 K * tc(CI)/N§ 14.29 ns C3 tf(CO) Fall time, CLKOUT 3 ns C4 tr(CO) Rise time, CLKOUT 3 ns C5 tw(COL) Pulse duration, CLKOUT low K * tc(CI)/2N − 1 K * tc(CI)/2N + 1 ns C6 tw(COH) Pulse duration, CLKOUT high K * tc(CI)/2N − 1 K * tc(CI)/2N + 1 ns § N = Clock frequency synthesis factor. K = divider ratio between CPU clock and system clock selected as CLKOUT. For example, when SYSCLK1 is selected as CLKOUT and SYSCLK1 is set to the CPU clock divided by four, use K = 4. |
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