HC705E5GRSSLASHD datasheet(101/148 Pages) NXP

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Synchronous Serial Interface (SSI)

SSI Registers

MC68HC705E5 — Rev. 1.0

General Release Specification

Synchronous Serial Interface (SSI)

LSBF — Least Significant Bit First

The LSBF bit determines the format of the data transfer. The two

formats are least significant bit (LSB) or most significant bit (MSB)

transferred or received first. Reset clears this bit, initializing the SSI to

MSB first order.

1 = Data will be sent and received in an LSB first format.

0 = Data will be sent and received in an MSB first format.

MSTR — Master Mode

Reset clears this bit and configures the SSI for slave operation. MSTR

may be set at any time regardless of the state of SE.

1 = SSI is configured for master mode. The transmission is initiated

by a write to the data register and the SCK pin becomes an

output providing a synchronous data clock at a rate determined

by the SR bit.

0 = SSI is configured to slave mode. Any transmission in progress

is aborted. Transfers are initiated by an external master which

should supply the clock signal to the SCK pin.

CPOL — Clock Polarity

The clock polarity bit controls the state of the SCK pin between

transmissions.

1 = SCK will be high between transmissions.

0 = SCK will be low between transmissions.

In both cases, the data is latched on the rising edge of SCK for serial

input and is valid on the rising edge of SCK for serial output. Reset

sets this bit.

SDIR — Serial Data Direction

When the SE bit = 1, SDIR functions as the output driver enable bit

for the SDIO pin with SSI in master or in slave mode. This bit has no

effect on the SDIO pin when the SSI is disabled (SE = 0). This bit is

cleared by reset.

1 = Enable the output driver of the SDIO pin.

0 = Disable the output driver of the SDIO pin.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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