CC1110-RTR1 datasheet(119/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 119 of 202

13.7.2.5 ADC Conversion Results

The

digital

conversion

result

represented in two's complement form.

For 13-bit resolution, the digital conversion

result is 8191 when the analogue input is

equal to the VREF, and the conversion

result is -8192 when the analogue input is

equal to –VREF, where VREF is the

selected positive voltage reference.

The digital conversion result is available

when ADCCON1.EOC is set to 1, in ADCH

and ADCL.

When the ADCCON2.SCH bits are read,

they will indicate which channel the

conversion result in ADCL and ADCH apply

to.

13.7.2.6 ADC Reference Voltage

The

positive

reference

voltage

for

analogue-to-digital

conversions

selectable

either

internally

generated 1.25V voltage, the AVDD pin,

the external voltage applied to the AIN7

input pin or the differential voltage applied

to the AIN6-AIN7 inputs.

It is possible to select the reference

voltage as the input to the ADC in order to

perform a conversion of the reference

voltage e.g. for calibration purposes.

Similarly, it is possible to select the ground

terminal GND as an input.

13.7.2.7 ADC Conversion Timing

The 26 MHz crystal oscillator should be

selected when the ADC is used. The ADC

runs on a clock which is the 26 MHz

system clock source divided by 6 to give a

4.33 MHz ADC clock. The delta sigma

modulator and decimation filter both use

the ADC clock for their calculations.

The time required to perform a conversion

depends on the selected decimation rate.

When the decimation rate is set to for

instance 128, the decimation filter uses

exactly 128 of the ADC clock periods to

calculate the result. When a conversion is

started, the input multiplexer is allowed 16

ADC clock cycles to settle in case the

channel has been changed since the

previous conversion. The 16 clock cycles

settling time applies to all decimation

rates. Thus in general, the conversion time

is given by:

Tconv = (decimation rate + 16) x 0.23 µs

13.7.2.8 ADC Interrupts

The ADC will generate an interrupt when

an extra conversion has completed. An

interrupt

not

generated

when

conversion

from

the

sequence

completed.

13.7.2.9 ADC DMA Triggers

The ADC will generate a DMA trigger

every

time

conversion

from

the

sequence has completed. When an extra

conversion completes, no DMA trigger is

generated.

There is one DMA trigger for each of the

eight channels defined by the first eight

possible settings for ADCCON2.SCH . The

DMA trigger is active when a new sample

is ready from the conversion for the

channel. The DMA triggers are named

ADC_CHx in Table 37 on page 84.

In addition there is one DMA trigger,

ADC_CHALL, which is active when new

data is ready from any of the channels in

the ADC conversion sequence.

13.7.2.10 ADC Registers

This section describes the ADC registers.

ADCL (0xBA) – ADC Data Low

Bit

Name

Reset

R/W

Description

7:2

ADC[5:0]

0x00

Least significant part of ADC conversion result.

1:0

Not used. Always read as 0

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