CC1110-RTR1 datasheet(123/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 123 of 202

13.8 Random Number Generator

13.8.1 Introduction

The random number generator has the

following features.

•

Generate pseudo-random bytes which

can be read by the CPU or used

directly by the Command Strobe

Processor.

•

Calculate CRC16 of bytes that are

written to RNDH.

•

Seeded by a random bit-stream from

the delta-sigma modulator in the ADC.

•

Seeded by value written to RNDL.

The random number generator is a 16-bit

Linear Feedback Shift Register (LFSR)

with polynomial

(i.e.

CRC16). It uses different levels of

unrolling depending on the operation it

performs. The basic version (no unrolling)

is shown below.

in_bit

Figure 21: Basic structure of the Random Number Generator

The random number generator is turned

off when ADCCON1.RCTRL=”11”.

13.8.2 Random

Number

Generator

Operation

The operation of the random number

generator

controlled

through

combination of the ADCCON1.RCTRL bits

and input signals from other modules. The

current value of the 16-bit shift register in

the LFSR can be read from the RNDH and

RNDL registers.

13.8.2.1 Semi random sequence

generation

The

default

operation

(ADCCON1.RCTRL=”00”) is to clock the

LFSR once (13x unrolling) each time the

Command Strobe Processor reads the

random value. This leads to the availability

of a fresh pseudo-random byte from the

LSB end of the LFSR.

Another way to update the LFSR is to set

ADCCON1.RCTRL=”01”. This will clock

the LFSR once (no unrolling) and the

ADCCON1.RCTRL bits will automatically be

cleared

when

the

operation

has

completed.

13.8.2.2 Seeding

When a true random value is required, the

LFSR can be seeded with random bits

from the delta-sigma modulator. For

seeding

option,

the

ADC

must

performing a conversion, so the actual

seeding will not start until the ADC is

running. This seeding process is started

by setting ADCCON1.RCTRL=”10”. When

the seeding has completed, these bits are

automatically cleared.

The LFSR can also be seeded from

software by simply writing to the RNDL

is written, the 8 LSB of the LFSR is copied

to the 8 MSB and the 8 LSBs are replaced

with the new data byte that was written to

RNDL.

13.8.2.3 CRC16

The LFSR can also be used to calculate

the CRC value of a sequence of bytes.

Writing to the RNDH register will trigger a

CRC

calculation.

The

new

byte

processed from the MSB end and an 8x

unrolling is used, so that a new byte can

be written to RNDH every clock cycle.

Note that the LFSR must be properly

seeded by writing to RNDL, before the

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