CC1110-RTR1 datasheet(136/203 Pages) TI

136 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 136 of 202

WDCTL.EN stops the timer and writing 1

restarts the timer from 0x0000.

The

timer

interval

set

the

WDCTL.INT[1:0] bits. In timer mode, a

reset will not be produced when the timer

interval has been reached.

13.12.3 Watchdog Timer Example

Figure 27 shows an example of periodical

clearing of an active watchdog timer.

; clear watchdog timer

MOV

WDCTL,#ABh

MOV

WDCTL,#5Bh

Figure 27: WDT Example

13.12.4 Watchdog Timer Register

This section describes the register for the

Watchdog Timer.

WDCTL (0xC9) – Watchdog Timer Control

Bit

Name

Reset

R/W

Description

7:4

CLR[3:0]

0000

R/W

Clear timer. When 0xA followed by 0x5 is written to these bits, the

timer is loaded with 0x0. Note the timer will only be cleared when

0x5 is written within 0.5 watchdog clock period after 0xA was

written. Writing to these bits when

EN is 0 has no effect. These

bits are always be read as 0000.

Enable timer. When a 1 is written to this bit the timer is enabled

and starts incrementing. Writing a 0 to this bit in timer mode stops

the timer. Writing a 0 to this bit in watchdog mode has no effect.

Timer disabled (stop timer)

R/W

Timer enabled

Mode select. This bit selects the watchdog timer mode.

Watchdog mode

MODE

R/W

Timer mode

Timer interval select. These bits select the timer interval defined as

a given number of 32.768 or 34 kHz oscillator periods.

clock period x 32768 (typical 1 s)

clock period x 8192 (typical 0.25 s)

clock period x 512 (typical 15.625 ms)

1:0

INT[1:0]

R/W

clock period x 64 (typical 1.9 ms)

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