CC1110-RTR1 datasheet(138/203 Pages) TI

138 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 138 of 202

The number of stop bits to be transmitted

is set to one or two bits determined by the

always check for one stop bit. If the first

stop bit received during reception is not at

the expected stop bit level, a framing error

signaled

setting

bit

UxCSR.FE high. UxCSR.FE is cleared

when UxCSR is read. The receiver will

check both stop bits when UxUCR.SPB is

set.

13.13.2 SPI Mode

This section describes the SPI mode of

operation for synchronous communication.

In SPI mode, the USART communicates

with an external system through a 3-wire

or 4-wire interface. The interface consists

of the pins MOSI, MISO, SCK and SS_N.

Refer to section 13.1 for description of

how the USART pins are assigned to the

I/O pins.

The SPI mode includes the following

features:

•

3-wire and 4-wire SPI interface

•

Master and slave modes

•

Configurable SCK polarity and phase

•

Configurable LSB or MSB first transfer

The

SPI

mode

selected

when

UxCSR.MODE is set to 0.

In SPI mode, the USART can be

configured to operate either as an SPI

master or as an SPI slave by writing the

UxCSR.SLAVE bit.

13.13.2.1 SPI Master Operation

An SPI byte transfer in master mode is

initiated when the UxDBUF register is

written. The USART generates the SCK

serial clock using the baud rate generator

(see section 13.13.3) and shifts the

provided byte from the transmit register

onto the MOSI output. At the same time

the receive register shifts in the received

byte from the MISO input pin.

The UxCSR.ACTIVE bit goes high when

the transfer starts and low when the

transfer ends. When the transfer ends, the

UxCSR.RX_BYTE and UxCSR.TX_BYTE

bits are set. A receive interrupt is

generated when new received data is

ready

the

UxDBUF

USART

Receive/Transmit Data register.

The polarity and clock phase of the serial

clock SCK is selected by UxGCR.CPOL

and UxGCR.CPHA as shown in Figure 28.

The order of the byte transfer is selected

by the UxGCR.ORDER bit.

At the end of the transfer, the received

data byte is available for reading from the

UxDBUF.

A transmit interrupt is generated when the

unit is ready to accept another data byte

for transmission. Since UxDBUF is double-

buffered, this happens just after the

transmission has been initiated.

13.13.2.2 SPI Slave Operation

An SPI byte transfer in slave mode is

controlled by the external system. The

data on the MISO input is shifted into the

receive register controlled by the serial

clock SCK which is an input in slave

mode. At the same time the byte in the

transmit register is shifted out onto the

MOSI output.

The UxCSR.ACTIVE bit goes high when

the transfer starts and low when the

transfer ends. Then the UxCSR.RX_BYTE

and UxCSR.TX_BYTE bits are set and a

receive interrupt is generated.

The expected polarity and clock phase of

SCK is selected by UxGCR.CPOL and

UxGCR.CPHA as shown in Figure 28. The

expected order of the byte transfer is

selected by the UxGCR.ORDER bit.

At the end of the transfer, the received

data byte is available for reading from

UxDBUF

The transmit interrupt is generated at the

start of the operation.

CC1110-RTR1 데이터시트(PDF) 138 Page - Texas Instruments

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