CC1110-RTR1 datasheet(147/203 Pages) TI

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CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 147 of 202

13.14 Flash Controller

The

CC1110 contains 32 KB flash memory

for storage of program code. The flash

memory is programmable from the user

software.

The Flash Controller handles writing and

erasing the embedded 32 KB flash

memory. The embedded flash memory

consists of 32 pages of 1024 bytes each.

The flash memory is byte-addressable

from

the

CPU

and

16-bit

word-

programmable.

The flash controller has the following

features:

•

16-bit word programmable

•

Page erase

•

Lock bits for write-protection and code

security

•

Flash erase timing 20 ms

•

Flash write timing 20 µs

13.14.1 Flash Write

Data is written to the flash memory by

using a program command initiated by

writing the Flash Control register, FCTL.

Flash write operations can program any

number of locations in the flash memory at

a time – it is however important to make

sure the pages to be written are erased

first.

A write operation is performed using one

out of two methods;

•

Through DMA transfer

•

Through CPU SFR access.

The DMA transfer method is the preferred

way to write to the flash memory.

A write operation is initiated by writing a 1

to FCTL.WRITE. The address to start

writing at, is given by FADDRH:FADDRL.

During

each

single

write

operation

FCTL.SWBSY is set high. During a write

operation the data written to the FWDATA

The

flash

memory

16-bit

word-

programmable, meaning data is written as

16-bit words. Therefore the actual writing

to flash memory takes place each time two

bytes have been written to FWDATA.

The CPU will not be able to access the

flash, e.g. to read program code, while a

flash write operation is in progress.

Therefore the program code executing the

flash write must be executed from RAM,

meaning that the program code must

reside in the area 0xF000 to 0xFF00 in

CODE memory space.

When a flash write operation is executed

from RAM, the CPU continues to execute

code from the next instruction after the

write to FWDATA, which initiated the flash

write operation.

The FCTL.SWBSY bit must be 0 before

accessing the flash after a flash write,

otherwise an access violation occurs. This

also means that FCTL.SWBSY must be 0

before program execution can continue at

a location in flash memory i.e. from the

area 0x0000 to 0x7FFF in CODE memory

space.

13.14.1.1 DMA Flash Write

When using DMA write operations, the

data to be written into flash is stored in

DATA/XDATA memory. A DMA channel is

configured to read the data to be written

from memory and write this data to the

Flash Write Data register, FWDATA with the

DMA trigger event FL enabled. Thus the

Flash Controller will trigger a DMA transfer

when the Flash Write Data register,

FWDATA, is ready to receive new data. The

DMA channel should be configured to

perform a block to fixed, single mode, byte

size transfers.

When the DMA channel is armed, starting

a flash write will trigger the first DMA

transfer.

Figure 29 shows an example how a DMA

channel is configured and how a DMA

transfer is initiated to write a block of data

from a location in XDATA to flash memory.

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