CC1110-RTR1 datasheet(149/203 Pages) TI

149 / 203 page

CC1110

CC1110 PRELIMINARY Datasheet (Rev. 1.01) SWRS033A

Page 149 of 202

13.14.1.2 CPU Flash Write

The CPU can also write directly to the

flash. The CPU writes data to the Flash

Write Data register, FWDATA. The flash

memory is written each time two bytes

have been written to FWDATA. The CPU

can poll the FCTL.SWBSY status to

determine when the flash is ready for two

more bytes to be written to FWDATA..

Performing flash write from XDATA

The steps required to start a flash write

operation from XDATA are shown in

Figure 30 on page 149.

Disable interrupts

BUSY=1?

Setup FCTL, FWT,

FADDRH, FADDRL

Write FWDATA

YES

; Write 32-bit word from XDATA

; Assumes 26 MHz system clock is used

;

CLR

;mask interrupts

C1:

MOV

A,FCTL

;wait until flash controller is ready

ACC.7,C1

MOV

FADDRH,#00h

;setup flash address high

MOV

FADDRL,#01h

;setup flash address low

MOV

FWT,#2Ah

;setup flash timing

MOV

FCTL,#02h

;set flash page write

MOV

FWDATA,#12h

;first byte

MOV

FWDATA,#34h

;second byte, initiates write

Figure 30 : Flash write performed from XDATA

13.14.2 Flash Page Erase

A page erase is initiated by setting

FCTL.ERASE to 1. The page addressed

by FADDRH[6:1] is erased when a page

erase is initiated. Note that if a page erase

is initiated simultaneously with a page

write, i.e. FCTL.WRITE is set to 1, the

page erase will be performed before the

page write operation. The FCTL.BUSY bit

can be polled to see when the page erase

has completed.

Note: if flash erase operations are

performed from within flash memory and

the watchdog timer is enabled, a watchdog

timer interval must be selected that is

longer than 20 ms, the duration of the

flash erase operation, so that the CPU will

manage to clear the watchdog timer.

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