HCS08 datasheet(222/290 Pages) MOTOROLA

222 / 290 page

Analog-to-Digital Converter (ATD) Module

MC9S08GB/GT

222

MOTOROLA

14.1 Introduction

The ATD module is an analog-to-digital converter with a successive approximation register (SAR)

architecture with sample and hold.

14.1.1 Features

•

8-/10-bit resolution

•

14.0

µsec, 10-bit single conversion time at a conversion frequency of 2 MHz

•

Left-/right-justified result data

•

Left-justified signed data mode

•

Conversion complete flag or conversion complete interrupt generation

•

Analog input multiplexer for up to eight analog input channels

•

Single or continuous conversion mode

14.1.2 Modes of Operation

The ATD has two modes for low power

•

Stop mode

•

Power-down mode

14.1.2.1 Stop Mode

When the MCU goes into stop mode, the MCU stops the clocks and the ATD analog circuitry is turned

off, placing the module into a low-power state. Once in stop mode, the ATD module aborts any single or

continuous conversion in progress. Upon exiting stop mode, no conversions occur and the registers have

their previous values. As long as the ATDPU bit is set prior to entering stop mode, the module is

reactivated coming out of stop.

14.1.2.2 Power Down Mode

Clearing the ATDPU bit in register ATDC also places the ATD module in a low-power state. The ATD

conversion clock is disabled and the analog circuitry is turned off, placing the module in power-down

mode. (This mode does not remove power to the ATD module.) Once in power-down mode, the ATD

module aborts any conversion in progress. Upon setting the ATDPU bit, the module is reactivated. During

power-down mode, the ATD registers are still accessible.

Note that the reset state of the ATDPU bit is zero. Therefore, the module is reset into the power-down state.

14.1.3 Block Diagram

Figure 14-2 illustrates the functional structure of the ATD module.

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