APEX20KC datasheet(53/90 Pages) ALTERA

53 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 30. APEX 20KC JTAG Waveforms

Table 16 shows the JTAG timing parameters and values for APEX 20KC

devices.

f For more information, see the following documents:

■

Application Note 39 (IEEE Std. 1149.1 (JTAG) Boundary-Scan Testing in

Altera Devices)

Table 16. APEX 20KC JTAG Timing Parameters & Values

Symbol

Parameter

Min

Max

Unit

tJCP

TCK

clock period

100

tJCH

TCK

clock high time

tJCL

TCK

clock low time

tJPSU

JTAG port setup time

tJPH

JTAG port hold time

tJPCO

JTAG port clock to output

tJPZX

JTAG port high impedance to valid output

tJPXZ

JTAG port valid output to high impedance

tJSSU

Capture register setup time

tJSH

Capture register hold time

tJSCO

Update register clock to output

tJSZX

Update register high impedance to valid output

tJSXZ

Update register valid output to high impedance

TDO

TCK

tJPZX

JPCO

tJPH

t JPXZ

tJCP

tJPSU

t JCL

tJCH

TDI

TMS

Signal

to Be

Captured

Signal

to Be

Driven

JSZX

tJSSU

tJSH

JSCO

tJSXZ

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