APEX20KC datasheet(4/90 Pages) ALTERA

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Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Notes to Tables 3 and 4:

(1)

I/O counts include dedicated input and clock pins.

(2)

APEX 20KC device package types include plastic quad flat pack (PQFP), 1.27-mm

pitch ball-grid array (BGA), and 1.00-mm pitch FineLine BGATM packages.

(3)

This device uses a thermally enhanced package, which is taller than the regular

package. Consult the Altera Device Package Information Data Sheet for detailed

package size information.

General

Description

Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer

the MultiCore architecture, which combines the strengths of LUT-based

and product-term-based devices with an enhanced memory structure.

LUT-based logic provides optimized performance and efficiency for data-

path, register-intensive, mathematical, or digital signal processing (DSP)

designs. Product-term-based logic is optimized for complex

combinatorial paths, such as complex state machines. LUT- and product-

term-based logic combined with memory functions and a wide variety of

MegaCore and AMPP functions make the APEX 20KC architecture

uniquely suited for SOPC designs. Applications historically requiring a

combination of LUT-, product-term-, and memory-based devices can now

be integrated into one APEX 20KC device.

Table 4. APEX 20KC FineLine BGA Package Options & I/O Count Notes (1), (2)

Device

484 Pin

672 Pin

1,020 Pin

EP20K200C

376

EP20K400C

488 (3)

EP20K600C

508 (3)

588

EP20K1000C

508 (3)

708

Table 5. APEX 20KC QFP & BGA Package Sizes

Feature

208-Pin PQFP

240-Pin PQFP

356-Pin BGA

652-Pin BGA

Pitch (mm)

0.50

1.27

Area (mm2)

924

1,218

1,225

2,025

Length

× Width (mm × mm)

30.4

× 30.4

34.9

× 34.9

35.0

× 35.0

45.0

× 45.0

Table 6. APEX 20KC FineLine BGA Package Sizes

Feature

484 Pin

672 Pin

1,020 Pin

Pitch (mm)

1.00

Area (mm2)

529

729

1,089

Length

× Width (mm × mm)

× 23

× 27

× 33

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