APEX20KC datasheet(9/90 Pages) ALTERA

9 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

MegaLAB Structure

APEX 20KC devices are constructed from a series of MegaLABTM

structures. Each MegaLAB structure contains 16 logic array blocks (LABs),

one ESB, and a MegaLAB interconnect, which routes signals within the

MegaLAB structure. In EP20K1000C devices, MegaLAB structures

contain 24 LABs. Signals are routed between MegaLAB structures and

I/O pins via the FastTrack interconnect. In addition, edge LABs can be

driven by I/O pins through the local interconnect. Figure 2 shows the

MegaLAB structure.

Figure 2. MegaLAB Structure

Logic Array Block

Each LAB consists of 10 LEs, the LEs’ associated carry and cascade chains,

LAB control signals, and the local interconnect. The local interconnect

transfers signals between LEs in the same or adjacent LABs, IOEs, or ESBs.

The Quartus II Compiler places associated logic within an LAB or adjacent

LABs, allowing the use of a fast local interconnect for high performance.

Figure 3 shows the APEX 20KC LAB.

APEX 20KC devices use an interleaved LAB structure. This structure

allows each LE to drive two local interconnect areas, minimizing the use

of the MegaLAB and FastTrack interconnect and providing higher

performance and flexibility. Each LE can drive 29 other LEs through the

fast local interconnect.

ESB

MegaLAB Interconnect

Local

Interconnect

To Adjacent

LAB or IOEs

LABs

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

LE1

LE2

LE3

LE4

LE5

LE6

LE7

LE8

LE9

LE10

APEX20KC 데이터시트(PDF) 9 Page - Altera Corporation

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