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APEX20KC 데이터시트(PDF) 71 Page - Altera Corporation |
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APEX20KC 데이터시트(HTML) 71 Page - Altera Corporation |
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71 / 90 page ![]() Altera Corporation 71 APEX 20KC Programmable Logic Device Data Sheet Notes to Tables 40 and 41: (1) These timing parameters are sample-tested only. (2) For more information, refer to Table 43. Tables 42 and 43 define the timing delays for each I/O standard. Some output standards require test load circuits for AC timing measurements as shown in Figures 36 through 38. Table 41. APEX 20KC External Bidirectional Timing Parameters Note (1) Symbol Parameter Condition tINSUBIDIR Setup time for bidirectional pins with global clock at LAB-adjacent input register tINHBIDIR Hold time for bidirectional pins with global clock at LAB-adjacent input register tOUTCOBIDIR Clock-to-output delay for bidirectional pins with global clock at IOE register (2) tXZBIDIR Synchronous output enable register to output buffer disable delay (2) tZXBIDIR Synchronous output enable register to output buffer enable delay (2) tINSUBIDIRPLL Setup time for bidirectional pins with PLL clock at LAB-adjacent input register tINHBIDIRPLL Hold time for bidirectional pins with PLL clock at LAB-adjacent input register tOUTCOBIDIRPLL Clock-to-output delay for bidirectional pins with PLL clock at IOE register (2) tXZBIDIRPLL Synchronous output enable register to output buffer disable delay with PLL (2) tZXBIDIRPLL Synchronous output enable register to output buffer enable delay with PLL (2) Table 42. APEX 20KC Selectable I/O Standard Input Adder Delays (Part 1 of 2) Note (1) Symbol Parameter Condition LVCMOS Input adder delay for the LVCMOS I/O standard LVTTL Input adder delay for the LVTTL I/O standard 2.5 V Input adder delay for the 2.5-V I/O standard 1.8 V Input adder delay for the 1.8-V I/O standard PCI Input adder delay for the PCI I/O standard GTl+ Input adder delay for the GTL+ I/O standard SSTL-3 Class I Input adder delay for the SSTL-3 Class I I/O standard SSTL-3 Class II Input adder delay for the SSTL-3 Class II I/O standard SSTL-2 Class I Input adder delay for the SSTL -2 Class I I/O standard SSTL-2 Class II Input adder delay for the SSTL -2 Class II I/O standard |
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