APEX20KC datasheet(31/90 Pages) ALTERA

31 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Read/Write Clock Mode

The read/write clock mode contains two clocks. One clock controls all

registers associated with writing: data input, WE, and write address. The

other clock controls all registers associated with reading: read enable

(RE), read address, and data output. The ESB also supports clock enable

and asynchronous clear signals; these signals also control the read and

write registers independently. Read/write clock mode is commonly used

for applications where reads and writes occur at different system

frequencies. Figure 20 shows the ESB in read/write clock mode.

Figure 20. ESB in Read/Write Clock Mode

Note (1)

Note to Figure 20:

(1)

All registers can be cleared asynchronously by ESB local interconnect signals, global signals, or the chip-wide reset.

Dedicated Clocks

ENA

data[ ]

ress[ ]

RAM/ROM

128

× 16

256

× 8

512

× 4

1,024

× 2

2,048

× 1

Data In

Address

Write Enable

Data Out

utclken

nclken

nclock

utclock

Write

Pulse

Generator

wren

Dedicated Inputs &

Global Signals

To MegaLAB,

FastTrack &

Local

Interconnect

APEX20KC 데이터시트(PDF) 31 Page - Altera Corporation

APEX20KC 데이터시트(HTML) 31 Page - Altera Corporation

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