APEX20KC datasheet(28/90 Pages) ALTERA

28 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Figure 16. APEX 20KC Parallel Expanders

Embedded

System Block

The ESB can implement various types of memory blocks, including

dual-port RAM, ROM, FIFO, and CAM blocks. The ESB includes input

and output registers; the input registers synchronize writes, and the

output registers can pipeline designs to improve system performance. The

ESB offers a dual-port mode, which supports simultaneous reads and

writes at two different clock frequencies. Figure 17 shows the ESB block

diagram.

Figure 17. ESB Block Diagram

32 Signals from

Local Interconnect

To Next

Macrocell

From

Macrocell

Product-

Term

Select

Matrix

Product-

Term

Select

Matrix

Macrocell

Product-

Term Logic

Macrocell

Product-

Term Logic

Parallel

Expander Switch

Parallel

Expander Switch

wraddress[]

data[]

wren

inclock

inclocken

inaclr

rdaddress[]

q[]

rden

outclock

outclocken

outaclr

APEX20KC 데이터시트(PDF) 28 Page - Altera Corporation

APEX20KC 데이터시트(HTML) 28 Page - Altera Corporation

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