APEX20KC datasheet(70/90 Pages) ALTERA

70 / 90 page

Altera Corporation

APEX 20KC Programmable Logic Device Data Sheet

Tables 40 and 41 describe APEX 20KC external timing parameters. The

timing values for these pin-to-pin delays are reported for all pins using the

3.3-V LVTTL I/O standard.

Table 39. APEX 20KC Minimum Pulse Width Timing Parameters

Symbol

Parameter

tCH

Minimum clock high time from clock pin

tCL

Minimum clock low time from clock pin

tCLRP

LE clear pulse width

tPREP

LE preset pulse width

tESBCH

Clock high time

tESBCL

Clock low time

tESBWP

Write pulse width

tESBRP

Read pulse width

Table 40. APEX 20KC External Timing Parameters

Note (1)

Symbol

Clock Parameter

Conditions

tINSU

Setup time with global clock at IOE register

tINH

Hold time with global clock at IOE register

tOUTCO

Clock-to-output delay with global clock at IOE output register

(2)

tINSUPLL

Setup time with PLL clock at IOE input register

tINHPLL

Hold time with PLL clock at IOE input register

tOUTCOPLL

Clock-to-output delay with PLL clock at IOE output register

(2)

APEX20KC 데이터시트(PDF) 70 Page - Altera Corporation

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