WM8944BECSSLASHR datasheet(53/165 Pages) CIRRUS

53 / 165 page

WM8944B

Rev 4.3

OUTPUT SIGNAL PATHS ENABLE

Each analogue output pin can be independently enabled or disabled using the register bits described

in Table 31. The speaker PGA and mixers can also be controlled.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R3 (03h)

Power

management

OUT_ENA

LINEOUT enable

0 = Disabled

1 = Enabled

SPK_PGA_ENA

Speaker PGA enable

0 = Disabled

1 = Enabled

SPKN_SPKVDD_

ENA

SPKOUTN enable

0 = Disabled

1 = Enabled

Note that SPKOUTN is also

controlled by SPKN_OP_ENA.

When powering down SPKOUTN,

the SPKN_SPKVDD_ENA bit

should be reset first.

SPKP_SPKVDD_

ENA

SPKOUTP enable

0 = Disabled

1 = Enabled

Note that SPKOUTP is also

controlled by SPKP_OP_ENA.

When powering down SPKOUTP,

the SPKP_SPKVDD_ENA bit

should be reset first

SPKN_OP_ENA

SPKOUTN enable

0 = Disabled

1 = Enabled

Note that SPKOUTN is also

controlled by

SPKN_SPKVDD_ENA. When

powering up SPKOUTN, the

SPKN_OP_ENA bit should be

enabled first.

SPKP_OP_ENA

SPKOUTP enable

0 = Disabled

1 = Enabled

Note that SPKOUTP is also

controlled by

SPKP_SPKVDD_ENA. When

powering up SPKOUTP, the

SPKP_OP_ENA bit should be

enabled first

SPK_MIX_ENA

Speaker output mixer enable

0 = Disabled

1 = Enabled

Table 31 Output Signal Paths Enable

To enable the output PGA and mixers, the reference voltage VMID and the bias current must also be

enabled. See “Reference Voltages and Master Bias” for details of the associated controls VMID_SEL

and BIAS_ENA.

Note that the Line output, Speaker outputs, Speaker PGA mixer and Speaker PGA are all muted by

default. The required signal paths must be un-muted using the control bits described in the respective

tables below.

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