WM8944BECSSLASHR datasheet(60/165 Pages) CIRRUS

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WM8944B

Rev 4.3

LDO REGULATOR

The WM8944B provides an internal LDO which provides a regulated voltage for use as an internal

supply and reference, which can also be used to power external circuits.

The LDO is enabled by setting the LDO_ENA register bit. The LDO supply is drawn from the LDOVDD

pin; the LDO output is provided on the LDOVOUT pin. The LDO requires a reference voltage and a

bias source; these are configured as described below.

The LDO bias source (master bias or start-up bias) is selected using BIAS_SRC. Care is required

during start-up to ensure that the selected bias is enabled; the master bias will not normally be

available at initial start-up, and the start-up bias should be selected in the first instance.

The LDO reference voltage can be selected using LDO_REF_SEL; this allows selection of either the

internal bandgap reference or one of the VMID resistor strings. When VMID is selected as the

reference, then LDO_REF_SEL_FAST selects either the Normal VMID reference or the Fast-Start

VMID reference. Care is required during start-up to ensure that the selected reference is enabled; the

VMID references are enabled using VMID_ENA and VMID_FAST_START as described in Table 40

and Table 41 respectively.The internal bandgap reference is nominally 1.5V. Note that this value is

not trimmed and may vary significantly (+/-10%) between different devices. When using this reference,

the internal bandgap reference must be enabled by setting the BG_ENA register, as described in

Table 37. The bandgap voltage can be adjusted using the BG_VSEL register as described in Table

39.

The LDO output voltage is set using the LDO_VSEL register, which sets the ratio of the output voltage

to the LDO reference voltage. See Table 38 for LDO output voltages.

Example1:

How to generate an LDOVOUT voltage of 3.0V from a 3.3V LDOVDD supply voltage.

If VMID is selected as the reference voltage for the LDO (LDO_REF_SEL = 0) then the VMID voltage

must be supplied from LDOVDD (VMID_REF_SEL = 0) and the VMID ratio set to 5/11 (VMID_CTRL =

0). This gives VMID = 1.5V.

The default LDO_VSEL gives LDOVOUT = Vref * 1.97 = 1.5V * 1.97 = 2.96V (see Table 38).

Example2:

Generating an LDOVOUT voltage of 2.4V from a 3.0V LDOVDD supply.

For maximum signal swing the VMID voltage should be half of the LDOVOUT voltage. For LDOVOUT

of 2.4V the optimum VMID voltage is 1.2V. Select the VMID source voltage as LDOVOUT

(VMID_REF_SEL = 1) and the VMID ratio as 1/2 (VMID_CTRL = 1). This gives VMID = 1.2V.

VMID cannot be used as the LDO reference voltage so use the Bandgap voltage as the LDO

reference voltage (LDO_REF_SEL = 1, BG_ENA = 1). The default Bandgap voltage is 1.467V. For

LDOVOUT of 2.4V LDOVSEL should be set to 2.4V / 1.467V = 1.636. Referring to Table 38

LDO_VSEL = 03h will give LDOVOUT = 1.467 * 1.66 = 2.435V.

Note that the Bnadgap voltage is not trimmed so if required the Bandgap voltage can be changed

(BG_VSEL

– see Table 39) to get closer to the required voltage.

By default, the LDO output is actively discharged to GND through internal resistors when the LDO is

disabled. This is desirable in shut-down to prevent any external connections being affected by the

internal circuits. The LDO output can be set to float when the LDO is disabled; this is selected by

setting the LDO_OP_FLT bit. This option should be selected if the LDO is bypassed and an external

voltage is applied to LDOVOUT.

The LDO output is monitored for voltage accuracy. The LDO undervoltage status can be read at any

time from the LDO_UV_STS bit, as described in Table 37. This bit can be polled at any time, or may

output directly on a GPIO pin, or may be used to generate Interrupt events.

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