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WM8944BECS/R 데이터시트(PDF) 70 Page - Cirrus Logic

부품명 WM8944BECS/R
상세설명  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8944BECS/R 데이터시트(HTML) 70 Page - Cirrus Logic

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WM8944B
70
Rev 4.3
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
1 BCLK
Falling edge can occur anywhere in this area
1 BCLK
Figure 25 DSP/PCM Mode Audio Interface (mode A, LRCLK_INV=1, Slave)
n
n-1
n-2
3
2
1
n
n-1
n-2
3
2
1
LEFT CHANNEL
RIGHT CHANNEL
MSB
LSB
Input Word Length (WL)
1/fs
LRCLK
BCLK
DACDAT/
ADCDAT
1 BCLK
1 BCLK
Falling edge can occur anywhere in this area
Figure 26 DSP/PCM Mode Audio Interface (mode B, LRCLK_INV=1, Slave)
COMPANDING
The WM8944B supports A-law and
-law companding on both transmit (ADC) and receive (DAC)
sides as shown in Table 46. Companding converts 13 bits (
-law) or 12 bits (A-law) to 8 bits using
non-linear quantization. This provides greater precision for low-amplitude signals than for
high-amplitude signals, resulting in a greater usable dynamic range than 8 bit linear quantization.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R5 (05h)
Companding
control
3
DAC_COMP
0
DAC Companding Enable
0 = Disabled
1 = Enabled
2
DAC_COMPMO
DE
0
DAC Companding Mode
0 = µ-law
1 = A-law
1
ADC_COMP
0
ADC Companding Enable
0 = Disabled
1 = Enabled
0
ADC_COMPMO
DE
0
ADC Companding Mode
0 = µ-law
1 = A-law
Table 46 Companding Control



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