WM8944BECSSLASHR datasheet(68/165 Pages) CIRRUS

68 / 165 page

WM8944B

Rev 4.3

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

LRCLK_INV

LRCLK Polarity / DSP Mode A-B

select.

Left Justified and I2S modes

–

LRCLK polarity

0 = Not Inverted

1 = Inverted

DSP Mode

– Mode A-B select

0 = MSB is available on 2nd BCLK

rising edge after LRCLK rising edge

(mode A)

1 = MSB is available on 1st BCLK

rising edge after LRCLK rising edge

(mode B)

3:2

WL [1:0]

Digital Audio Interface Word Length

00 = 16 bits

01 = 20 bits

10 = 24 bits

11 = 32 bits

Note

– see “Companding” for the

selection of 8-bit mode.

1:0

FMT [1:0]

Digital Audio Interface Format

00 = Reserved

01 = Left Justified

10 = I2S format

11 = DSP/PCM mode

R21 (15h)

DAC Control 1

DAC_DATINV

DAC Data Invert

0 = DAC output not inverted

1 = DAC output inverted

R25 (19h)

ADC Control 1

ADCR_DATINV

Right DMIC Data Invert

0 = Right DMIC output not inverted

1 = Right DMIC output inverted

ADCL_DATINV

ADC / Left DMIC Data Invert

0 = ADC / Left DMIC output not

inverted

1 = ADC / Left DMIC inverted

Table 45 Audio Data Format Control

In Left Justified mode, the MSB is available on the first rising edge of BCLK following a LRCLK

transition. The other bits up to the LSB are then transmitted in order. Depending on word length,

BCLK frequency and sample rate, there may be unused BCLK cycles before each LRCLK transition.

n-1

n-2

n-1

n-2

LEFT CHANNEL

RIGHT CHANNEL

MSB

LSB

Input Word Length (WL)

1/fs

LRCLK

BCLK

DACDAT/

ADCDAT

Figure 21 Left Justified Audio Interface (assuming n-bit word length)

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