WM8944BECSSLASHR datasheet(72/165 Pages) CIRRUS

72 / 165 page

WM8944B

Rev 4.3

The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted

for

-law, all even data bits are inverted for A-law). Companded data is transmitted in the first 8 MSBs

of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4 bits), as

shown in Table 47.

BIT7

BIT[6:4]

BIT[3:0]

SIGN

EXPONENT

MANTISSA

Table 47 8-bit Companded Word Composition

8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows

samples to be passed using as few as 8 BCLK cycles per Left/Right Clock frame. When using DSP

mode B, 8-bit data words may be transferred consecutively every 8 BCLK cycles.

8-bit

mode

(without

Companding)

may

enabled

setting

DAC_COMPMODE=1

ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0.

AUDIO INTERFACE LOOPBACK

A loopback function is provided for test and evaluation purposes. When the LOOPBACK register bit is

set, the DAC input data is fed through the DSP Core to the Left ADC output, as illustrated in Figure

29.

Note that this is only possible when ADCL_ENA = 1 and ADCR_ENA = 0. There is no output on the

Right ADC channel when the Audio Interface Loopback is enabled.

DIGITAL AUDIO

INTERFACE

ADC

DAC

Audio Interface

Loopback Mode

SE1 (LPF/HPF,

3D surround, 5-notch, DF1)

SE2 (HPF,

Re-Tune, 5-band EQ)

SE3 (Dynamic

Range Control)

Figure 29 Audio Interface Loopback

WM8944BECS/R 데이터시트(PDF) 72 Page - Cirrus Logic

WM8944BECS/R 데이터시트(HTML) 72 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL