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WM8944BECS/R 데이터시트(PDF) 56 Page - Cirrus Logic

부품명 WM8944BECS/R
상세설명  Mono Low-Power CODEC with Video Buffer
PDF  165 Pages
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제조업체  CIRRUS [Cirrus Logic]
홈페이지  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM8944BECS/R 데이터시트(HTML) 56 Page - Cirrus Logic

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WM8944B
56
Rev 4.3
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
9
IN1_TO_PGA_AT
TEN
0
IN1 to Speaker PGA Mixer
attenuation
0 = 0dB
1 = -6dB attenuation
6
BYP_TO_PGA_A
TTEN
0
Input PGA (ADC bypass) to
Speaker PGA Mixer attenuation
0 = 0dB
1 = -6dB attenuation
3
DAC_TO_PGA_A
TTEN
0
DAC to Speaker PGA Mixer
attenuation
0 = 0dB
1 = -6dB attenuation
0
AUX_TO_PGA_A
TTEN
0
AUX to Speaker PGA Mixer
attenuation
0 = 0dB
1 = -6dB attenuation
Table 33 Speaker PGA Mixer (MIXSPK) Control
SPEAKER PGA VOLUME CONTROL
The volume control of the Speaker PGA can be adjusted using the SPK_VOL register field as
described in Table 34. The gain range is -57dB to +6dB in 1dB steps.
Note that the output from the Speaker PGA Volume control is an input to the Speaker Output control
described in the following section.
To prevent "zipper noise", a zero-cross function is provided on the Speaker PGA. When this feature is
enabled, volume updates will not take place until a zero-crossing is detected.
Note that any dc offset in the DAC data should be less than the peak data to ensure there are zero-
crossings.
The Speaker PGA volume control register fields are described in Table 34.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
R47 (2Fh)
SPK volume
ctrl
7
SPK_ZC
0
Speaker PGA Zero Cross Detector
0 = Change gain immediately
1 = Change gain on zero cross only
6
SPK_PGA_MUTE
1
Speaker PGA Mute
0 = Disable Mute
1 = Enable Mute
5:0
SPK_VOL [5:0]
11_1001
(0dB)
Speaker PGA Volume
00_0000 = -57dB gain
00_0001 = -56dB
…
11_1001 = 0dB
...
11_1111 = +6dB
(See Table 35 for volume range)
Table 34 Speaker PGA Volume Control



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