WM8944BECSSLASHR datasheet(38/165 Pages) CIRRUS

38 / 165 page

WM8944B

Rev 4.3

The SE2 ‘enable’ bits are described in Table 14. Note that (with the exception of the SE2 HPF) other

control fields must also be determined and written to the WM8944B

using WISCE™ or other tools.

The registers described below only allow the sub-blocks of SE2 to be enabled or disabled.

Note that it is not recommended to access these control fields unless appropriate values have been

written to the associated bits in registers R99 to R175.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R99 (63h)

SE2_HPF_CO

NFIG

SE2_HPF_R_E

SE2 Right channel High-pass filter

enable

0 = Disabled

1 = Enabled

SE2_HPF_L_EN

SE2 Left channel High-pass filter

enable

0 = Disabled

1 = Enabled

R100 (64h)

SE2_RETUNE

_CONFIG

SE2_RETUNE_

R_ENA

SE2 Right channel ReTune filter

enable

0 = Disabled

1 = Enabled

SE2_RETUNE_

L_ENA

SE2 Left channel ReTune filter

enable

0 = Disabled

1 = Enabled

R133 (85h)

SE2_5BEQ_C

ONFIG

SE2_5BEQ_L_E

SE2 Left channel 5-band EQ enable

0 = Disabled

1 = Enabled

Table 14 Signal Enhancement Block 2 (SE2)

The register controls for Signal Enhancement Block SE3 are defined in the “Dynamic Range Control

(DRC)

” section.

DYNAMIC RANGE CONTROL (DRC)

The dynamic range controller (DRC) is a circuit which can be enabled in the digital playback or digital

record path of the WM8944B, depending upon the selected DSP mode. The function of the DRC is to

adjust the signal gain in conditions where the input amplitude is unknown or varies over a wide range,

e.g. when recording from microphones built into a handheld system.

The DRC can apply Compression and Automatic Level Control to the si

gnal path. It incorporates ‘anti-

clip’ and ‘quick release’ features for handling transients in order to improve intelligibility in the

presence of loud impulsive noises.

The DRC also incorporates a Noise Gate function, which provides additional attenuation of very low-

level input signals. This means that the signal path is quiet when no signal is present, giving an

improvement in background noise level under these conditions.

The DRC is enabled as described in Table 15. The audio signal path controlled by the DRC depends

upon the selected DSP Configuration mode - see

“DSP Core” for details.

If the DRC is used in the record path then to remove any DC offset from the input signal the ADC high

pass filter must be enabled. The ADC HPF is enabled when ADC_HPF = 1. This is the default

condition. The DRC will not function correctly if there is any DC offset..

WM8944BECS/R 데이터시트(PDF) 38 Page - Cirrus Logic

WM8944BECS/R 데이터시트(HTML) 38 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL