WM8944BECSSLASHR datasheet(22/165 Pages) CIRRUS

22 / 165 page

WM8944B

Rev 4.3

ANALOGUE INPUT SIGNAL PATH

The WM8944B has two analogue input pins, which may be selected in different configurations. The

analogue input paths can support line and microphone inputs, in single-ended or pseudo-differential

modes. The analogue inputs IN1/DMICDAT AUX may be configured as inputs to the input PGA or to

the output mixers as single-ended or differential signals.

The input PGA (PGA) is routed to the Analogue to Digital converter (ADC). There is also a bypass

path, enabling the signal to be routed directly to the output mixers.

The WM8944B input signal paths and control registers are illustrated in Figure 8.

WM8944B

IN1/DMICDAT

INPGA

AUX

Digital Mic Interface

DMICCLK

(GPIO)

DMICDAT

INPGA_ENA

INPGA_VOL[5:0]

ADCL_VOL[7:0]

ADC_HPF_MODE

ADC_HPF_SR[1:0]

ADC_HPF_CUT[1:0]

ADC_HPF

AUX_TO_N_INPGA

P_INPGA_SEL[1:0]

ADCL_ENA

DMIC_ENA

IN1

AUX

BYPASS

ADC L

ADC /

Record

Digital

Filters

Figure 8 Input Signal Paths

INPUT PGA ENABLE

The input PGA (Programmable Gain Amplifier) is enabled using the register bit INPGA_ENA, as

described in Table 1.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R2 (02h)

Power

Management 1

INPGA_ENA

Input PGA Enable

0 = Disabled

1 = Enabled

Table 1 Input PGA Enable

To enable the input PGA, the reference voltage VMID and the bias current must also be enabled. See

“Reference Voltages and Master Bias” for details of the associated controls VMID_SEL and

BIAS_ENA.

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