WM8944BECSSLASHR datasheet(64/165 Pages) CIRRUS

64 / 165 page

WM8944B

Rev 4.3

requires the analogue bias current to be enabled throughout the signal path prior to the VMID

reference voltage being applied. The WM8944B incorporates pop-suppression circuits which address

these requirements.

An alternate bias current source (Start-Up Bias) is provided for pop-free start-up; this is enabled by the

STARTUP_BIAS_ENA register bit. The start-up bias is selected (in place of the Master bias) using the

BIAS_SRC bit. It is recommended that the start-up bias is used during start-up, before switching back

to the higher quality, normal bias.

A soft-start circuit is provided in order to control the switch-on of the VMID reference. The soft-start

control circuit offers two slew rates for enabling the VMID reference; these are selected and enabled

by VMID_RAMP. When the soft-start circuit is enabled prior to enabling VMID_SEL, the reference

voltage rises smoothly, without the step change that would otherwise occur. It is recommended that

the soft-start circuit and the output signal path be enabled before VMID is enabled by VMID_SEL.

A soft shut-down is provided, using the soft-start control circuit and the start-up bias current generator.

The soft shut-down of VMID is achieved by setting VMID_RAMP, STARTUP_BIAS_ENA and

BIAS_SRC to select the start-up bias current and soft-start circuit prior to setting VMID_SEL=00.

The internal LDO (described in the previous section) requires a voltage reference. Under normal

operating conditions, this is provided from VMID, via the register controls described in Table 40. Note,

however, that VMID is normally generated from the LDO output. Therefore, an alternative voltage

reference

required

for

start-up,

which

not

dependent

the

LDO

output.

The

VMID_FAST_START bit enables a ‘Fast-Start’ reference powered from LDOVDD. This alternate VMID

can be selected as the LDO reference using the LDO_REF_SEL_FAST bit as described in Table 37.

The VMID soft-start and fast start register controls are defined in Table 41.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R7 (07h)

Additional

control

VMID_FAST_STA

VMID (fast-start) Enable

0 = Disabled

1 = Enabled

STARTUP_BIAS_

ENA

Start-Up Bias Enable

0 = Disabled

1 = Enabled

BIAS_SRC

Bias Source select

0 = Master bias

1 = Start-Up bias

6:5

VMID_RAMP [1:0]

VMID soft start enable / slew rate

control

00 = Disabled

01 = Fast soft start

10 = Normal soft start

11 = Slow soft start

Table 41 Soft Start Control

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