L6986I_V01 datasheet(16/60 Pages) STMICROELECTRONICS

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4.7

Output voltage line regulation

All results shown in this section come from measurements performed using the reference schematic depicted in

figure below.

Figure 15. Schematic used for line and load regulation tests

Primary output line regulation

The regulator features an enhanced primary line regulation due to the peak current mode architecture. Figure 16

shows negligible output voltage variation (normalized to the value measured at VIN = 12 V) over an input voltage

range up to 24 V for L6986I with VOUT prim = 5.3 V.

Figure 16. Primary line regulation

-0.5%

-0.4%

-0.3%

-0.2%

-0.1%

0.0%

VIN [V]

Iout_prim = 0A

Iout_prim = 1A

Secondary output line regulation

The secondary output line regulation is defined, similarly to the primary side, as the variation of secondary the

output voltage due to the input voltage change at a specific current. The secondary output line regulation is mainly

affected by the transformer and in particular by its leakage inductance.

Keeping constant the leakage inductance (i.e. using the same transformer), an higher input voltage allows to

slightly increase the isolated output voltage, as shown in figure below.

L6986I

Output voltage line regulation

DS13647 - Rev 2

page 16/60

L6986I 데이터시트(PDF) 16 Page - STMicroelectronics