PIFE32251B-R47MS datasheet(18/96 Pages) TI1

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TPS65094

SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Specifications

(1)

Frequency of transient load current ranges from 0 to 1 MHz with duty cycle of 50%. For cases where duty cycle and frequency are

limited by tr and tf, the highest frequency is set by 1 / (tr + tf), where tr is rise time (0% to 100%) and tf is fall time (100% to 0%).

5.8

Electrical Characteristics: Synchronous Buck Converters

over recommended input voltage range, TA = –40°C to +85°C and TA = 25°C for typical values (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

BUCK3

VIN

Power input voltage

4.5

5.5

VOUT

DC output voltage

Step size

BUCK3_VID[6:0] = 0000000

BUCK3_VID[6:0] = 0000001

0.65

BUCK3_VID[6:0] = 0000010

0.675

⋮

BUCK3_VID[6:0] = 0010001 (default)

1.05

⋮

BUCK3_VID[6:0] = 1110101

3.55

BUCK3_VID[6:0] = 1110110–1111111

3.575

DC output voltage

accuracy

VOUT = 1.05 V, IOUT = 1.5 A

–2%

VOUT = 1.05 V, IOUT = 100 mA

–2.5%

2.5%

SR(VOUT)

Output DVS slew rate

2.5

3.125

mV/µs

IOUT

Continuous DC output

current

IIND_LIM

HSD FET current limit

4.3

Quiescent current

VIN = 5 V, VOUT = 1 V

µA

ΔVOUT/ΔVIN

Line regulation

VOUT = 1.05 V, IOUT = 1.5 A

–0.5%

0.5%

ΔVOUT/ΔIOUT

Load regulation

VIN = 5 V, VOUT = 1.05 V, IOUT = 0 A to 3 A,

referenced to VOUT at IOUT = 1.5 A

–0.2%

ΔVOUT_TR

(1)

Load transient

regulation

DC + AC at sense point,

VIN = 5 V, VOUT = 1.05 V, IOUT = 0.9 A to 3 A and 3 A

to 0.9 A with slew rate of 2.5 A/µs

–5%

VTH_PG

Power Good

deassertion threshold

in percentage of

target VOUT

VOUT rising

108%

VOUT falling

92%

VTH_HYS_PG

Power Good

reassertion hysteresis

entering back into

VTH_PG

VOUT rising or falling

LSW

Output inductance

0.376

0.47

0.564

µH

CIN

Input bypass

capacitance

2.5

µF

COUT

Output filtering

capacitance

61.6

110

µF

RDIS

Output auto-discharge

resistance

BUCK3_DIS[1:0] = 01

100

BUCK3_DIS[1:0] = 10

200

BUCK3_DIS[1:0] = 11

500

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