PIFE32251B-R47MS datasheet(79/96 Pages) TI1

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TPS65094

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SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Application and Implementation

7.2.2.2.2 Selecting the Output Capacitors

TI recommends using ceramic capacitors with low-ESR values are recommended to provide the lowest

output voltage ripple. The output capacitor requires either an X7R or an X5R rating. Y5V and Z5U

capacitors, aside from the wide variation in capacitance overtemperature, become resistive at high

frequencies.

At light load currents, the converter operates in PFM mode and the output voltage ripple is dependent on

the output-capacitor value and the PFM peak inductor current. Higher output-capacitor values minimize

the voltage ripple in PFM mode. To achieve specified regulation performance and low output voltage

ripple, the DC-bias characteristic of ceramic capacitors must be considered. The effective capacitance of

ceramic capacitors drops with increasing DC-bias voltage.

For the output capacitors of the BUCK converters, TI recommends placing small ceramic capacitors

between the inductor and load with many vias to the PGND plane. This solution typically provides the

smallest and lowest-cost solution available for DCAP2 controllers.

To meet the transient specifications, the output capacitance must equal or exceed the minimum

capacitance listed for BUCK3, BUCK4, and BUCK5 (assuming quality layout techniques are followed).

7.2.2.2.3 Selecting the Input Capacitors

Due to the nature of the switching converter with a pulsating input current, a low-ESR input capacitor is

required for best input-voltage filtering and for minimizing the interference with other circuits caused by

high input-voltage spikes. For the PVINx pin, 2.5 µF of input capacitance (after derating) is required for

most applications. A ceramic capacitor is recommended to achieve the low-ESR requirement. However,

the voltage rating and DC-bias characteristic of ceramic capacitors must be considered. For better input-

voltage filtering, the input capacitor can be increased without any limit.

NOTE

Use the correct value for the ceramic capacitor capacitance after derating to achieve the

recommended input capacitance.

The preferred capacitor for the converters is one Samsung CL05A106MP5NUNC: 10 µF, 0402, 10 V,

±20%, or similar capacitor.

7.2.2.3

LDO Design Procedure

The VTT LDO must handle the fast load transients from the DDR memory for termination. Therefore, TI

recommends using ceramic capacitors to maintain a high amount of capacitance with low ESR on the VTT

LDO outputs and inputs. The preferred output capacitors for the VTT LDO are the GRM188R60J226MEA0

from Murata (22 µF, 0603, 6.3 V, ±20%, or similar capacitors). The preferred input capacitor for the VTT

LDO is the CL05A106MP5NUNC from Samsung (10 µF, 0402, 10 V, ±20%, or similar capacitor).

The remaining LDOs must have input and output capacitors chosen based on the values in Section 5.9,

Electrical Characteristics: LDOs.

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