PIFE32251B-R47MS datasheet(65/96 Pages) TI1

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TPS65094

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SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

Table 6-36. VR_CTRL3 Register Field Descriptions

Bit

Field

Type

Reset

Description

SWB1_2_DISABLEB

R/W

SWB1_2 Active Low Disable Bit. Writing 0 to this bit forces

SWB1_2 to turn off regardless of status of enable pins (PMICEN,

SLP_Sx). Has priority over SWB1_2_EN.

0: Disabled

1: SWB1_2 operates normally.

SWA1_DISABLEB

R/W

SWA1 Active Low Disable Bit. Writing 0 to this bit forces SWA1 to

turn off regardless of status of enable pins (PMICEN, SLP_Sx).

Has priority over SWA1_EN.

0: Disabled

1: SWA1 operates normally.

VTT_DISABLEB

R/W

TPS650940,

TPS650944, and

TPS650945: 0

TPS650941 and

TPS650942: 1

VTT_LDO Active Low Disable Bit. Writing 0 to this bit forces

VTT_LDO to turn off regardless of status of enable pins

(PMICEN, SLP_Sx). Has priority over VTT_EN.

0: Disabled

1: VTT_LDO operates normally.

VTT_EN

R/W

TPS650940,

TPS650944 and

TPS650945: 1

TPS650941 and

TPS650942: 0

VTT_LDO Enable bit. VTT_DISABLEB has priority over VTT_EN.

0: VTT_LDO operates normally.

1: Enabled regardless of power sequencing, unless

VTT_DISABLEB = 0

SWB1_2_EN

R/W

SWB1_2_Enable bit. SWB1_2_DISABLEB has priority over

SWB1_2_EN.

0: SWB1_2 operates normally.

1: Enabled regardless of power sequencing, unless

SWB1_2_DISABLEB = 0

LDOA3_EN

R/W

LDOA3 Enable bit.

0: Enabled if LDOLS_EN = 1

1: Enabled regardless of LDOLS_EN state

6.6.26 GPO_CTRL: GPO Control Register (offset = A1h) [reset = 0010 0000]

Figure 6-44. GPO_CTRL Register (offset = A1h) [reset = 0010 0000]

Bit

Bit Name

RESERVED

GPO_LVL

RESERVED

TPS65094x

Access

R/W

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 6-37. GPO_CTRL Register Field Descriptions

Bit

Field

Type Reset

Description

GPO_LVL

R/W

Open-drain GPO output level bit.

0: The pin is driven to logic low.

1: The pin is high impedance.

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