 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
PIFE32251B-R47MS 데이터시트(PDF) 47 Page - Texas Instruments |
|
|
|||||||||||||||||||||||||||||
PIFE32251B-R47MS 데이터시트(HTML) 47 Page - Texas Instruments |
|
|
47 / 96 page  S0 SLP_S0B VTT BUCK1 (VNN) S0 BUCK2 (VCCGI) SLP_S3B PCH_PWROK S3 SWB1_2 (2) T8 S3 S5/S4 SLP_S4B BUCK6 (VDDQ) T5 1.8 V 1.05 V VID ˜ 100 µs 0 V ˜ 5 ms 0 V SET VID by Host BUCK3 (VCCRAM) 0 V SWB1_2 (V1P8U) (1) ˜ 2 ms 30 ms to 60 ms (1) LPDDR3 and LPDDR4 (2) DDR3L 47 TPS65094 www.ti.com SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019 Submit Documentation Feedback Product Folder Links: TPS65094 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated 6.3.5.5 S0 to S4/5 Entry and Exit Assertion of the SLP_S4B (H → L) after the S3 entry pushes the sequence further down to S4/5 where SWB1_2 (for LPDDR3 or LPDDR4) and BUCK6 are disabled. Any rails not shown are essentially the same as the S0 to S3 entry and exit case described in Figure 6-11. Figure 6-11. S4/5 Entry and Exit Sequence |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
