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PIFE32251B-R47MS 데이터시트(PDF) 64 Page - Texas Instruments

부품명 PIFE32251B-R47MS
상세설명  PMIC for Intel Apollo Lake Platform
PDF  96 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

PIFE32251B-R47MS 데이터시트(HTML) 64 Page - Texas Instruments

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TPS65094
SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: TPS65094
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
Table 6-35. VR_CTRL2 Register Field Descriptions (continued)
Bit
Field
Type
Reset
Description
5
BUCK6_EN
R/W
0
BUCK6 Enable bit.
0: BUCK6 operates normally.
1: Enabled regardless of power sequencing
4
BUCK5_EN
R/W
0
BUCK5 Enable bit.
0: BUCK5 operates normally.
1: Enabled regardless of power sequencing
3
BUCK4_EN
R/W
0
BUCK4 Enable bit.
0: BUCK4 operates normally.
1: Enabled regardless of power sequencing
2
BUCK3_EN
R/W
0
BUCK3 Enable bit. BUCK3_DISABLEB has priority over BUCK3_EN.
0: BUCK3 operates normally.
1: Enabled regardless of power sequencing, unless BUCK3_DISABLEB = 0
1
BUCK2_EN
R/W
0
BUCK2 Enable bit. BUCK2_DISABLEB has priority over BUCK2_EN.
0: BUCK2 operates normally.
1: Enabled regardless of power sequencing, unless BUCK2_DISABLEB = 0
0
BUCK1_EN
R/W
0
BUCK1 Enable bit. BUCK1_DISABLEB has priority over BUCK1_EN.
0: BUCK1 operates normally.
1: Enabled regardless of power sequencing, unless BUCK1_DISABLEB = 0
6.6.25 VR_CTRL3: VR Enable/Disable Register (offset = 9Fh) [reset = 0111 0000]
Figure 6-43. VR_CTRL3 Register (Offset = 9Fh) [reset = 0111 0000]
Bit
7
6
5
4
3
2
1
0
Bit Name
RESERVED
SWB1_2_
DISABLEB
SWA1_
DISABLEB
VTT_
DISABLEB
VTT_EN
RESERVED
SWB1_2_EN
LDOA3_EN
TPS650940,
TPS650944, and
TPS650945
0
1
1
0
1
0
0
0
TPS650941 and
TPS650942
0
1
1
1
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset



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