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PIFE32251B-R47MS 데이터시트(PDF) 55 Page - Texas Instruments |
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PIFE32251B-R47MS 데이터시트(HTML) 55 Page - Texas Instruments |
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55 / 96 page ![]() 55 TPS65094 www.ti.com SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019 Submit Documentation Feedback Product Folder Links: TPS65094 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated 6.6.5 PMICSTAT: PMIC Status Register (offset = 04h) [reset = 0000 0000] Figure 6-23. PMICSTAT Register (offset = 04h) [reset = 0000 0000] Bit 7 6 5 4 3 2 1 0 Bit Name RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED SDIETEMP TPS65094x 0 0 0 0 0 0 0 0 Access R R R R R R R R LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-16. PMICSTAT Register Field Descriptions Bit Field Type Reset Description 0 SDIETEMP R 0 PMIC die temperature status. 0: PMIC die temperature is below THOT. 1: PMIC die temperature is above THOT. 6.6.6 OFFONSRC: PMIC Power Transition Event Register (offset = 05h) [reset = 0000 0000] Figure 6-24. OFFONSRC Register (offset = 05h) [reset = 0000 0000] Bit 7 6 5 4 3 2 1 0 Bit Name RESERVED RESERVED RESERVED RESERVED COLDOFF UVLO OCP CRITTEMP TPS65094x 0 0 0 0 0 0 0 0 Access R R R R R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-17. OFFONSRC Register Field Descriptions Bit Field Type Reset Description 3 COLDOFF R/W 0 Set by PMIC cleared by host. Host writes 1 to this bit to clear it. 0 = Cleared 1 = PMIC was shut down by host through PMIC_EN pin. 2 UVLO R/W 0 Set by PMIC cleared by host. Host writes 1 to this bit to clear it. 0 = Cleared 1 = PMIC was shut down due to a UVLO event (VSYS less 5.4 V). The setting of this bit sets the ONOFFSRC bit in the PMIC_IRQ register. 1 OCP R/W 0 Set by PMIC cleared by host. Host writes 1 to this bit to clear it. 0 = Cleared 1 = PMIC shut down due to a power fault event. The setting of this bit sets the ONOFFSRC bit in the PMIC_IRQ register. 0 CRITTEMP R/W 0 Set by PMIC cleared by host. Host writes 1 to this bit to clear it. 0 = Cleared 1 = PMIC shut down due to the rise of PMIC die temperature above critical temperature threshold (TCRIT). The setting of this bit sets the ONOFFSRC bit in the PMIC_IRQ register. |
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