PIFE32251B-R47MS datasheet(41/96 Pages) TI1

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TPS65094

www.ti.com

SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

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Detailed Description

(1)

When PMIC is first enabled, SLP_S4B and SLP_S3B are to be treated as if they are low (actual state of signal ignored) until the

deassertion of RSMRSTB (L

→ H).

(2)

When PMIC is first enabled, SLP_S0B are to be treated as if they are high (actual state of signal ignored) until the assertion of

PCH_PWROK (L

→ H).

(3)

THERMTRIPB is to be treated as if it is high (actual state of signal ignored) until the deassertion of RSMRSTB (L

→ H).

6.3.5

Power Sequencing and VR Control

When a valid power source is available at VSYS (VSYS

≥ 5.6 V), internal analog blocks including LDO5

and LDO3P3 are enabled. For part numbers with LDOA1 set as an always on rail, the PMIC leaves reset

and I2C communication is available as soon as LDO3P3 and LDO5 power goods are confirmed. For part

numbers with LDOA1 set as a general-purpose LDO, the PMIC remains in reset until PMICEN is set high.

Five input pins of the TPS65094x device are driven by a host or by external-controller (EC) defined power

states that transition from one to another in sequence.

Table 6-8 shows various system-level power states. Also, Table 6-9 summarizes a list of active rails in

each power state. The sequencing for the transitions between these states is described in the following

sections.

If a rail is either disabled by I2C or OTP programming, then it is not enabled by the following sequences.

For example, VTT LDO is not enabled for LPDDR4 OTPs.

Table 6-8. Power State and Corresponding I/O Status

POWER

STATE

SIGNALS TO PMIC

SIGNALS FROM PMIC

PMICEN

SLP_S4B(1)

SLP_S3B(1)

SLP_S0B(2)

THERMTRIPB(3)

RSMRSTB

PCH_PWROK

S4/S5

S0iX

(1)

For LPDDR3 and LPDDR4

(2)

For DDR3L

Table 6-9. Active Rails in Each Power State

POWER STATE

ACTIVE RAILS

S4/S5

BUCK1 (VNN), BUCK4 (V1P8A), BUCK5 (V1P24A)

Rails in S4/S5 + SWB1_2 (V1P8U)(1), BUCK6 (VDDQ)

Rails in S3 + SWB1_2(2), VTT, BUCK2 (VCCGI), BUCK3 (VCCRAM)

S0iX

Rails in S0 – BUCK1 (VNN), BUCK2 (VCCGI), BUCK3 (VCCRAM), VTT

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