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PIFE32251B-R47MS 데이터시트(PDF) 56 Page - Texas Instruments

부품명 PIFE32251B-R47MS
상세설명  PMIC for Intel Apollo Lake Platform
PDF  96 Pages
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제조업체  TI1 [Texas Instruments]
홈페이지  http://www.ti.com
Logo TI1 - Texas Instruments

PIFE32251B-R47MS 데이터시트(HTML) 56 Page - Texas Instruments

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TPS65094
SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019
www.ti.com
Submit Documentation Feedback
Product Folder Links: TPS65094
Detailed Description
Copyright © 2015–2019, Texas Instruments Incorporated
6.6.7
BUCK1CTRL: BUCK1 Control Register (offset = 20h) [reset = 0011 1000]
Figure 6-25. BUCK1CTRL Register (offset = 20h) [reset = 0011 1000]
Bit
7
6
5
4
3
2
1
0
Bit Name
RESERVED
BUCK1_VID[6]
BUCK1_VID[5]
BUCK1_VID[4]
BUCK1_VID[3]
BUCK1_VID[2]
BUCK1_VID[1]
BUCK1_VID[0]
TPS65094x
0
0
1
1
1
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-18. BUCK1CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
6–0
BUCK1_VID[6:0]
R/W
0111000
(1.05 V)
This field sets the BUCK1 regulator output regulation voltage in normal mode.
Default = 1.05 V. Note that 0 V is a valid setting and all Power Goods stay high
when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-3 for full
details.
6.6.8
BUCK2CTRL: BUCK2 Control Register (offset = 21h) [reset = 0000 0000]
Figure 6-26. BUCK2CTRL Register (offset = 21h) [reset = 0000 0000]
Bit
7
6
5
4
3
2
1
0
Bit Name
RESERVED
BUCK2_VID[6]
BUCK2_VID[5]
BUCK2_VID[4]
BUCK2_VID[3]
BUCK2_VID[2]
BUCK2_VID[1]
BUCK2_VID[0]
TPS65094x
0
0
0
0
0
0
0
0
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-19. BUCK2CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
6–0
BUCK2_VID[6:0]
R/W
0000000
(0 V)
This field sets the BUCK2 regulator output regulation voltage in normal mode.
Default = 0 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-3 for full
details.
6.6.9
BUCK3CTRL: BUCK3 Control Register (offset = 23h) [reset = 0001 0001]
Figure 6-27. BUCK3CTRL Register (offset = 23h) [reset = 0001 0001]
Bit
7
6
5
4
3
2
1
0
Bit Name
RESERVED
BUCK3_VID[6]
BUCK3_VID[5]
BUCK3_VID[4]
BUCK3_VID[3]
BUCK3_VID[2]
BUCK3_VID[1]
BUCK3_VID[0]
TPS65094x
0
0
0
1
0
0
0
1
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 6-20. BUCK3CTRL Register Field Descriptions
Bit
Field
Type Reset
Description
6–0
BUCK3_VID[6:0]
R/W
0010001
(1.05 V)
This field sets the BUCK3 regulator output regulation voltage in normal mode.
Default = 1.05 V. Note that 0 V is a valid setting and all Power Goods must stay
high when VID is set to 0x00 and (or) SLP_S0B goes low. See Table 6-4 for full
details.



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