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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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PIFE32251B-R47MS 데이터시트(PDF) 63 Page - Texas Instruments |
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PIFE32251B-R47MS 데이터시트(HTML) 63 Page - Texas Instruments |
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63 / 96 page  63 TPS65094 www.ti.com SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019 Submit Documentation Feedback Product Folder Links: TPS65094 Detailed Description Copyright © 2015–2019, Texas Instruments Incorporated 6.6.23 VR_CTRL1: BUCK1-3 Control Register (offset = 9Ch) [reset = 0000 0111] Figure 6-41. VR_CTRL1 Register (offset = 9Ch) [reset = 0000 0111] Bit 7 6 5 4 3 2 1 0 Bit Name RESERVED RESERVED BUCK3_MODE BUCK2_MODE BUCK1_MODE BUCK3_ DISABLEB BUCK2_ DISABLEB BUCK1_ DISABLEB TPS650940, TPS650941, TPS650942, and TPS650944 0 0 0 0 0 1 1 1 TPS650945 0 0 1 0 0 1 1 1 Access R R R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-34. VR_CTRL1 Register Field Descriptions Bit Field Type Reset Description 5 BUCK3_MODE R/W 0 This field sets the BUCK3 regulator operating mode. 0 = Automatic mode 1 = Forced PWM mode 4 BUCK2_MODE R/W 0 This field sets the BUCK2 regulator operating mode. 0 = Automatic mode 1 = Forced PWM mode 3 BUCK1_MODE R/W 0 This field sets the BUCK1 regulator operating mode. 0 = Automatic mode 1 = Forced PWM mode 2 BUCK3_DISABLEB R/W 1 BUCK3 Active Low Disable bit. Writing 0 to this bit forces BUCK3 to turn off regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over BUCK3_EN. 0: Disabled 1: BUCK3 operates normally. 1 BUCK2_DISABLEB R/W 1 BUCK2 Active Low Disable bit. Writing 0 to this bit forces BUCK2 to turn off regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over BUCK2_EN. 0: Disabled 1: BUCK2 operates normally. 0 BUCK1_DISABLEB R/W 1 BUCK1 Active Low DISABLE bit. Writing 0 to this bit forces BUCK1 to turn off regardless of status of enable pins (PMICEN, SLP_Sx). Has priority over BUCK1_EN. 0: Disabled 1: BUCK1 operates normally. 6.6.24 VR_CTRL2: VR Enable Register (offset = 9Eh) [reset = 0000 0000] Figure 6-42. VR_CTRL2 Register (offset = 9Eh) [reset = 0000 0000] Bit 7 6 5 4 3 2 1 0 Bit Name LDOA2_EN SWA1_EN BUCK6_EN BUCK5_EN BUCK4_EN BUCK3_EN BUCK2_EN BUCK1_EN TPS65094x 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 6-35. VR_CTRL2 Register Field Descriptions Bit Field Type Reset Description 7 LDOA2_EN R/W 0 LDOA2 Enable bit. 0: Enabled if LDOLS_EN = 1 1: Enabled regardless of LDOLS_EN state 6 SWA1_EN R/W 0 SWA1 Enable bit. 0: Enabled if LDOLS_EN pin or SWA1_EN pin = 1 1: Enabled regardless of LDOLS_EN or SWA1_EN state |
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