PIFE32251B-R47MS datasheet(83/96 Pages) TI1

83 / 96 page

BUCK2

BUCK3

BUCK5

BUCK4

BUCK1

BUCK6

VTT

VREF Capacitor

TPS65094

www.ti.com

SWCS133C – SEPTEMBER 2015 – REVISED FEBRUARY 2019

Submit Documentation Feedback

Product Folder Links: TPS65094

Layout

9.1

Layout Guidelines

For a detailed description regarding layout recommendations, refer to the TPS65094x Design Guide and

to the TPS65094x Schematic Checklist, Layout Checklist, and ILIM Calculator Tool. For all switching

power supplies, the layout is an important step in the design, especially at high peak currents and high

switching frequencies. If the layout is not carefully done, the regulator can have stability problems and EMI

issues. Therefore, use wide and short traces for the main current path and for the power ground tracks.

The input capacitors, output capacitors, and inductors must be placed as close as possible to the device.

Use a common-ground node for power ground and use a different, isolated node for control ground to

minimize the effects of ground noise. Connect these ground nodes close to the AGND pin by one or two

vias. Use of the design guide is highly encouraged in addition to the following list of other basic

requirements:

•

Do not allow the AGND, PGNDSNSx, or FBGND2 to connect to the thermal pad on the top layer.

•

To ensure proper sensing based on FET RDSON, PGNDSNSx must not connect to PGND until very

close to the PGND pin of the FET.

•

All inductors, input/output capacitors, and FETs for the converters and controller must be on the same

board layer as the device.

•

To achieve the best regulation performance, place feedback connection points near the output

capacitors and minimize the control feedback loop as much as possible.

•

Bootstrap capacitors must be placed close to the device.

•

The input and output capacitors of the internal reference regulators must be placed close to the device

pins.

•

Route DRVHx and SWx as a differential pair. Ensure that there is a PGND path routed in parallel with

DRVLx, which provides optimal driver loops.

9.2

Layout Example

Figure 9-1. EVM Layout Example With All Components on the Top Layer

PIFE32251B-R47MS 데이터시트(PDF) 83 Page - Texas Instruments

PIFE32251B-R47MS 데이터시트(HTML) 83 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96

데이터시트 다운로드

링크 URL